Microprocessor with time counter for statically dispatching instructions with phantom registers
AssigneeSimplex Micro, Inc.
InventorThang Minh Tran
Life of this patent
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Abstract
A processor includes a time counter and provides a method for statically dispatching fused instructions with first operation and second operation with preset execution times for forwarding of result data from the first operation to the second operation without writing to a register, and where the preset execution times are based on a time count from the time counter provided to an execution pipeline.
Claims23
A processor comprising:
- a time counter storing a time count representing a current time of the processor, wherein the time count is incremented periodically;
- an instruction issue unit coupled to the time counter for receiving a first fused instruction comprising a first operation that corresponds to a first instruction and a second operation that corresponds to a second instruction, wherein result data of the first operation are forwarded to the second operation without being stored in an intervening register, and issuing the first fused instruction with a preset execution time based on the time count;
- and
- an execution queue coupled to the time counter and the instruction issue unit to receive the first fused instruction from the instruction issue unit, and dispatch the first operation to a first functional unit when the preset execution time of the first operation corresponds to the time count and dispatch the second operation to a second functional unit when the preset execution time of the second operation corresponds to the time count, and wherein the result data from the first functional unit is forwarded to the second functional unit.
A processor comprising:
- a clock circuit;
- a time counter storing a time count representing a current time of the processor, wherein the time count is incremented with each cycle of the clock circuit;
- an instruction issue unit, coupled to the time counter, that receives a first fused instruction and that issues the first fused instruction with a preset execution time based on the time count, wherein the first fused instruction comprises a first operation and a second operation wherein result data of the first operation are forwarded to the second operation;
- an execution queue, coupled to the time counter and the instruction issue unit, to receive the first fused instruction from the instruction issue unit, and dispatch the first operation to a first functional unit when the preset execution time of the first operation is correlated to the time count and to dispatch the second operation to a second functional unit when the preset execution time of the second operation is correlated to the time count wherein the result data from the first functional unit is forwarded to the second functional unit;
- a register scoreboard storing a write time of a each register of a plurality of registers in a register file, wherein the write time is a future time based on the time count;
- an instruction decode unit coupled to the register scoreboard, wherein the instruction decode unit reads a write time for each source operand of the first operation of the first fused instruction from the register scoreboard, and uses each write time to determine the preset execution time for the first fused instruction;
- a time-resource matrix, coupled to the register scoreboard and the time counter, that stores information relating to available resources for each time count of the time counter;
- and
- wherein the available resources include at least one of:
- a plurality of read buses, a plurality of write buses, and a plurality of functional units.
A method for issuing a fused instruction with a first operation and a second operation to an execution queue in a processor to execute at a future time wherein the result data of the first operation is forwarded to the second operation without writing to a register of a register file and wherein the future time is time based on a time count from a time counter which is incremented with each cycle of a clock circuit.
Dependencies are inferred from the claim text.