# US 12,001,846 B2 · Systems, methods, and devices for queue availability monitoring

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- Number: US 12,001,846 B2
- Document ID: US12001846B2
- Status: Granted
- Kind: B2
- Application number: 17/963,189
- Filed: 2022-10-10
- Published: 2023-04-06
- Granted: 2024-06-04
- Earliest claimed: 2020-06-18
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Chao Yang; Wentao Wu; Glenn Yu; Wei Zhao; Fnu Vikram Singh; Xiaoyi Zhang; Yong Yang
- Web page: https://patentgrep.com/patent/US12001846B2

## CPC

- G06F 9/3856: {Reordering of instructions, e.g. using queues or age tags}
- G06F 3/0611: {in relation to response time}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 9/30018: {Bit or string instructions}
- G06F 9/3834: {Maintaining memory consistency}
- G06F 9/544: {Buffers; Shared memory; Pipes}
- G06F 11/3037: {where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00)}
- G06F 11/3051: {Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs (verification or detection of system hardware configuration G06F11/2247)}
- H04L 12/2807: {Exchanging configuration information on appliance services in a home automation network (arrangements for maintenance or administration involving network analysis for automatically determining the actual topology of a network H04L41/12; hardware or software tools for network management using graphical user interfaces H04L41/22; address allocation H04L61/50)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A method may include determining, with a queue availability module, that an entry is available in a queue, asserting a bit in a register based on determining that an entry is available in the queue, determining, with a processor, that the bit is asserted, and processing, with the processor, the entry in the queue based on determining that the bit is asserted. The method may further include storing the register in a tightly coupled memory associated with the processor. The method may further include storing the queue in the tightly coupled memory. The method may further include determining, with the queue availability module, that an entry is available in a second queue, and asserting a second bit in the register based on determining that an entry is available in the second queue. The method may further include finding the first bit in the register using a find first instruction.

## Claims

### Claim 1

A method comprising:
detecting, at a device, based at least in part on a doorbell indication, a first command for a protocol in a first command queue;
modifying a first portion of a register based on the detecting the first command;
detecting, at the device, a second command for the protocol in a second command queue;
modifying a second portion of the register based on the detecting the second command; and
processing, with a processor, the first command based on a status of the first portion of the register.

### Claim 2 (depends on 1)

The method of claim 1, further comprising storing the register in a memory associated with the processor.

### Claim 3 (depends on 2)

The method of claim 2, further comprising storing the first command queue in the memory associated with the processor.

### Claim 4 (depends on 1)

The method of claim 1, further comprising determining the first portion of the register using a find instruction.

### Claim 5 (depends on 1)

The method of claim 1, further comprising processing, with the processor, the second command based on the second portion of the register.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first command queue comprises a protocol queue, the method further comprising:
detecting, with a queue availability module, a third command in a direct memory access (DMA) queue; and
modifying a third portion of the register based on the detecting the third command in the DMA queue.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first command comprises a protocol command.

### Claim 8 (depends on 1)

The method of claim 1, wherein the processing the first command comprises managing a resource.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
receiving the first command using a communication interface;
parsing the first command; and
storing the first command in the first command queue.

### Claim 10 (depends on 1)

The method of claim 1, wherein the detecting the first command comprises checking a phase tag.

### Claim 11 (depends on 1)

The method of claim 1, wherein the first command queue comprises a priority command queue.

### Claim 12

A system comprising:
a first command queue;
a second command queue;
a register comprising a first portion to indicate, based at least in part on at least one doorbell indication, a first command for a protocol in the first command queue and a second portion to indicate, based at least in part on the at least one doorbell indication, a second command for the protocol in the second command queue; and
a storage device comprising a processor configured to process the first command based on a status of the first portion of the register.

### Claim 13 (depends on 12)

The system of claim 12, further comprising a queue availability module coupled to the processor using a system bus, wherein the register is stored on a processor side of the system bus.

### Claim 14 (depends on 12)

The system of claim 12, wherein the register is stored in a memory associated with the processor.

### Claim 15 (depends on 12)

The system of claim 12, wherein the processor is further configured to process the second command based on the second portion of the register.

### Claim 16 (depends on 15)

The system of claim 15, wherein the processor is further configured to check the register using a find instruction.

### Claim 17 (depends on 12)

The system of claim 12, wherein the register is a first register, the system further comprising a second register configured to duplicate at least a portion of the first register.

### Claim 18

A method comprising:
monitoring, at a device, a first command queue and a second command queue;
modifying a first portion of a register based, at least in part, on at least one doorbell indication and a first command for a protocol in the first command queue;
modifying a second portion of the register based, at least in part, on the at least one doorbell indication and a second command for the protocol in the second command queue; and
processing, with a processor at the device, the first command based on a state of the first portion of the register.

### Claim 19 (depends on 18)

The method of claim 18, further comprising storing the register in a memory associated with the processor.

### Claim 20 (depends on 18)

The method of claim 18, further comprising determining the first portion of the register using a find instruction.