# US 12,001,841 B2 · Content-addressable processing engine

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- Number: US 12,001,841 B2
- Document ID: US12001841B2
- Status: Granted
- Kind: B2
- Application number: 17/950,560
- Filed: 2022-09-22
- Published: 2023-02-02
- Granted: 2024-06-04
- Earliest claimed: 2021-01-15
- Assignees: Cornell University
- Applicants: Cornell University
- Inventors: José F. Martínez; Helena Caminal; Kailin Yang; Khalid Al-Hawaj; Christopher Batten
- Web page: https://patentgrep.com/patent/US12001841B2

## CPC

- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/3001: {Arithmetic instructions}
- G06F 9/30038: {using a mask}
- G06F 9/3004: {to perform operations on memory}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 15/7821: {Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A content-addressable processing engine, also referred to herein as CAPE, is provided. Processing-in-memory (PIM) architectures attempt to overcome the von Neumann bottleneck by combining computation and storage logic into a single component. CAPE provides a general-purpose PIM microarchitecture that provides acceleration of vector operations while being programmable with standard reduced instruction set computing (RISC) instructions, such as RISC-V instructions with standard vector extensions. CAPE can be implemented as a standalone core that specializes in associative computing, and that can be integrated in a tiled multicore chip alongside other types of compute engines. Certain embodiments of CAPE achieve average speedups of 14× (up to 254×) over an area-equivalent out-of-order processor core tile with three levels of caches across a diverse set of representative applications.

## Claims

### Claim 1

A content-addressable processing engine (CAPE) configured to execute a program having scalar operations and vector operations, the CAPE comprising:
a control processor configured to execute the scalar operations; and
a compute-storage block (CSB) configured to decode and execute the vector instructions associated with the vector operations in situ via sequences of content-addressable memory operations without assistance from arithmetic logic units (ALUs).

### Claim 2 (depends on 1)

The CAPE of claim 1, wherein the CSB is a co-processor of the control processor and comprises an array of content addressable parallel processing memories.

### Claim 3 (depends on 1)

The CAPE of claim 1, wherein the vector instructions reference program data within the CSB according to a predetermined list of available vector register identifiers specified in a CAPE instruction set architecture (ISA).

### Claim 4 (depends on 2)

The CAPE of claim 2, wherein the array of content-addressable parallel processing memories in the CSB comprises a plurality of subarrays, each subarray comprising rows of content-addressable memories.

### Claim 5 (depends on 4)

The CAPE of claim 4, wherein each row in one of the plurality of subarrays corresponds to a different bit of a vector element.

### Claim 6 (depends on 1)

The CAPE of claim 1, further comprising a vector memory unit (VMU) configured to interface with a memory external to the CAPE.

### Claim 7 (depends on 1)

The CAPE of claim 1, further comprising a vector control unit (VCU) configured to generate signal sequences for the CSB to execute the vector operations.

### Claim 8 (depends on 7)

The CAPE of claim 7, wherein non memory-access instructions route to the CSB through the VCU.

### Claim 9

An integrated circuit, comprising:
a content-addressable processing engine (CAPE) comprising an array of content-addressable parallel processing memories;
wherein:
the CAPE is configured to execute processing instructions comprising instructions for performing vector operations; and
the CAPE is configured to decode and carry out the instructions for executing vector operations in situ via sequences of content-addressable memory operations without assistance from arithmetic logic units (ALUs).

### Claim 10 (depends on 9)

The integrated circuit of claim 9, wherein the vector operations are performed according to a CAPE instruction set architecture (ISA).

### Claim 11 (depends on 9)

The integrated circuit of claim 9, wherein the CAPE is programmable using reduced instruction set computing (RISC) instructions.

### Claim 12 (depends on 11)

The integrated circuit of claim 11, wherein the CAPE is programmable using RISC-V or later instructions.

### Claim 13 (depends on 9)

The integrated circuit of claim 9, wherein:
the integrated circuit is a multi-core processor; and
the CAPE comprises a first core of the multi-core processor.

### Claim 14 (depends on 13)

The integrated circuit of claim 13, wherein the multi-core processor is configured to cause the CAPE to operate in a memory-only mode providing on-chip memory for other cores of the multi-core processor.

### Claim 15 (depends on 9)

The integrated circuit of claim 9, further comprising a central processing unit (CPU) core.

### Claim 16 (depends on 9)

The integrated circuit of claim 9, further comprising a graphic processing unit (GPU) core.

### Claim 17 (depends on 9)

The integrated circuit of claim 9, wherein the CAPE is configured to perform a first vector operation and a first scalar operation in parallel if there is no data dependency between the first vector operation and the first scalar operation.

### Claim 18

A method for executing a program using parallel processing in a content-addressable processing engine (CAPE), the method comprising:
receiving, at the CAPE, a set of processing instructions described by a general instruction set;
executing scalar operations from the set of processing instructions; and
decoding vector instructions from the set of processing instructions and executing corresponding vector operations in situ via content-addressable memory operations by an array of content-addressable parallel processing memories.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
generating signal sequences for operating the array of content-addressable parallel processing memories from the vector instructions described by the general instruction set; and
performing search and update operations using the signal sequences in a bit-parallel fashion across the array of content-addressable parallel processing memories.

### Claim 20 (depends on 18)

The method of claim 18, wherein the vector instructions reference program data according to a predetermined list of available vector register identifiers specified in the CAPE ISA.