# US 12,001,832 B2 · Chip having updating bus and reading bus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,001,832 B2 - Document ID: US12001832B2 - Status: Granted - Kind: B2 - Application number: 18/143,609 - Filed: 2023-05-05 - Published: 2023-08-31 - Granted: 2024-06-04 - Earliest claimed: 2020-12-29 - Applicants: PixArt Imaging Inc. - Inventors: Jr-Yi Li - Web page: https://patentgrep.com/patent/US12001832B2 ## CPC - G06F 8/65: Updates (security arrangements therefor G06F21/57) - G06F 9/4411: {Configuring for operating with peripheral devices; Loading of device drivers} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract There is provided a control chip including a microcontroller unit (MCU), a bus arbiter, a first bus, a second bus, a void hardware, a cache controller, a flash controller and a flash memory, wherein the flash memory is recorded with a firmware. When the MCU does not receive an update instruction, the bus arbiter reads, according to a function command of the MCU, a function return value associated with the function command from the flash memory via the first bus, the cache controller and the flash controller. When the MCU receives the update instruction, the bus arbiter updates the firmware in the flash memory via the second bus and the flash controller, and the void hardware actively replies a void return value associated with the function command to the MCU to replace the function return value. ## Claims ### Claim 1 A mouse chip, comprising: a flash memory, recorded with first firmware, and content of the flash memory being configured to operate a function called by the mouse chip to generate a function return value, wherein the mouse chip is configured to generate a function address of a function call, map the function address to an operation address, cache the function return value generated in the flash memory into a cache memory according to the operation address, and read the function return value in the cache memory via a first bus, or update the first firmware in the flash memory with update data via a second bus, different from the first bus, wherein upon not receiving an update instruction, the mouse chip is configured to read the function return value in the cache memory via the first bus, and upon receiving the update instruction, the mouse chip is configured to send the update data via the second bus to update the first firmware in the flash memory. ### Claim 2 (depends on 1) The mouse chip as claimed in claim 1, wherein upon receiving the update instruction, the mouse chip is further configured to generate and reply a void return value conforming to a format of the function return value of the function to replace the function return value. ### Claim 3 (depends on 2) The mouse chip as claimed in claim 2, wherein the mouse chip further comprises multiple registers configured to record the function address and a function return address of the function, and the mouse chip is further configured to change the function address and the function return address in the multiple registers upon receiving the update instruction. ### Claim 4 (depends on 3) The mouse chip as claimed in claim 3, wherein the multiple registers comprise a program counter register and a link register. ### Claim 5 (depends on 1) The mouse chip as claimed in claim 1, wherein the update instruction is generated by a mouse key or an external host. ### Claim 6 (depends on 1) The mouse chip as claimed in claim 1, further comprising at least one of a read only memory and a random access memory, wherein the read only memory or the random access memory is embedded with second firmware. ### Claim 7 (depends on 6) The mouse chip as claimed in claim 6, wherein the first firmware is configured as a driver of a third party's integrated circuit, and the second firmware is configured to calculate a mouse movement, and identify a mouse key click as well as a mouse roller rotation. ### Claim 8 (depends on 7) The mouse chip as claimed in claim 7, wherein upon sending the update data via the second bus, the second firmware continuously calculates the mouse movement, and identify the mouse key click as well as the mouse roller rotation. ### Claim 9 A chip, comprising: a flash memory, recorded with first firmware, and content of the flash memory being configured to operate a function called by the chip to generate a function return value, wherein the chip is configured to generate a function address of a function call, map the function address to an operation address, cache the function return value generated in the flash memory into a cache memory according to the operation address, read the function return value from the cache memory via a first bus, and stop reading the function return value from the cache memory via the first bus upon the first firmware in the flash memory being updated via a second bus, different from the first bus, wherein upon receiving an update instruction, the chip is further configured to generate and reply a void return value conforming to a format of the function return value of the function to replace the function return value. ### Claim 10 (depends on 9) The chip as claimed in claim 9, wherein the update instruction is generated by a mouse key or an external host. ### Claim 11 (depends on 9) The chip as claimed in claim 9, further comprising at least one of a read only memory and a random access memory, wherein the read only memory or the random access memory is embedded with second firmware. ### Claim 12 (depends on 11) The chip as claimed in claim 11, wherein the first firmware is configured as a driver of a third party's integrated circuit, and the second firmware is configured to calculate a mouse movement, and identify a mouse key click as well as a mouse roller rotation. ### Claim 13 (depends on 12) The chip as claimed in claim 12, wherein upon the first firmware in the flash memory being updated, the second firmware continuously calculates the mouse movement, and identify the mouse key click as well as the mouse roller rotation. ### Claim 14 A chip, comprising: a flash memory, recorded with first firmware, and content of the flash memory being configured to operate a function called by the chip to generate a function return value, wherein the chip is configured to read the function return value via a first bus, or update the first firmware in the flash memory via a second bus, different from the first bus, and generate a void return value conforming to a format of the function return value of the function to replace the function return value upon the first firmware in the flash memory being updated via the second bus, wherein the first firmware in the flash memory is updated when the chip receives an update instruction from a mouse key or an external host. ### Claim 15 (depends on 14) The chip as claimed in claim 14, wherein the chip further comprises multiple registers configured to record a function address and a function return address of the function, and the chip is further configured to change the function address and the function return address in the multiple registers upon the first firmware in the flash memory being updated via the second bus. ### Claim 16 (depends on 14) The chip as claimed in claim 14, further comprising at least one of a read only memory and a random access memory, wherein the read only memory or the random access memory is embedded with second firmware. ### Claim 17 (depends on 16) The chip as claimed in claim 16, wherein the second firmware is continuously operating when updating the first firmware in the flash memory via the second bus.