# US 12,001,774 B2 · Method to cure antenna violations in clock network using jumpers

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- Number: US 12,001,774 B2
- Document ID: US12001774B2
- Status: Granted
- Kind: B2
- Application number: 17/392,341
- Filed: 2021-08-03
- Published: 2023-02-09
- Granted: 2024-06-04
- Earliest claimed: 2021-08-03
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Amanda Christine Venton; Peter Milton Nasveschuk; Christopher Joseph Berry; Eric Chien Lai
- Web page: https://patentgrep.com/patent/US12001774B2

## CPC

- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 30/396: Clock trees
- H01Q 1/2283: {mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H01Q: ANTENNAS, i.e. RADIO AERIALS (radiators or antennas for microwave heating H05B6/72)

## Abstract

A method for curing antenna violations on an integrated circuit that includes multiple levels includes: obtaining a design of a circuit, the design including a first element connected to first device and a second element connected to one or more second devices, wherein the first and second elements both receive a common signal; determining that an antenna violation exists in on the first element at a first level of the multiple levels; and modifying the design of the circuit to add a connected between the first element and the second element at the first layer or at a layer below the first layer.

## Claims

### Claim 1

A method for curing antenna violations on an integrated circuit that includes multiple levels, the method comprising:
obtaining a design of a circuit, the design including multiple levels including a first level and a second level, a first element at the first level connected to a first device and a second element located on the second level connected to one or more second devices, wherein the first and second elements both receive a common clock signal, wherein the first device can discharge a first amount of a plasma induced charge and the one or more second device can discharge a second amount of plasma induced charge that is greater than the first amount;
determining that an antenna violation exists on the first level at the first element; and
modifying the design of the circuit to add a diode-less jumper connection between the first element and the second element so that the first device can discharge charge through the second device and cure the clock violation;
wherein the second level is below the first level.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first element is a via.

### Claim 3 (depends on 2)

The method of claim 2, wherein the second element is a metallization layer.

### Claim 4 (depends on 2)

The method of claim 2, wherein the second element is a via.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first element is a metallization layer and the second element is one of via or another metallization layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the integrated circuit is clock network and the common signal is clock signal.

### Claim 7

The method of 6, wherein the first device is one of a local clock buffer or a latch.

### Claim 8

A system comprising:
a memory having computer readable instructions; and
one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations for curing antenna violations on an integrated circuit that includes multiple levels comprising:
obtaining a design of a circuit, the design including multiple levels including a first level and a second level, a first element at the first level connected to a first device and a second element located on the second level connected to one or more second devices, wherein the first and second elements both receive a common clock signal, wherein the first device can discharge a first amount of a plasma induced charge and the one or more second device can discharge a second amount of plasma induced charge that is greater than the first amount;
determining that an antenna violation exists on the first level at the first element; and
modifying the design of the circuit to add a diode-less jumper connection between the first element and the second element so that the first device can discharge charge through the second device and cure the clock violation;
wherein the second level is below the first level.

### Claim 9 (depends on 8)

The system of claim 8, wherein the first element is a via.

### Claim 10 (depends on 8)

The system of claim 8, wherein the second element is a metallization layer or a via.

### Claim 11 (depends on 8)

The system of claim 8, wherein the integrated circuit is clock network and the common signal is clock signal.

### Claim 12 (depends on 10)

The system of claim 10, wherein the first device is one of a local clock buffer or a latch.

### Claim 13 (depends on 1)

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform the method of claim 1.