# US 12,001,773 B2 · Automated system and method for circuit design

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- Number: US 12,001,773 B2
- Document ID: US12001773B2
- Status: Granted
- Kind: B2
- Application number: 18/295,085
- Filed: 2023-04-03
- Published: 2023-07-27
- Granted: 2024-06-04
- Earliest claimed: 2021-05-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shin-Chi Chen; King-Ho Tam; Yu-Ze Lin; Huang-Yu Chen
- Web page: https://patentgrep.com/patent/US12001773B2

## CPC

- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/31: Design entry, e.g. editors specifically adapted for circuit design
- G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 2119/18: Manufacturability analysis or optimisation for manufacturability
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device, subject to a limiting condition, such as one determined using a cost function. A computer system including one or more EDAs configured to perform the method is also disclosed.

## Claims

### Claim 1

A method for optimizing a physical layout of an integrated circuit (IC) device, comprising:
(a) providing a plurality of values for an input variable parameter of the IC device;
(b) generating a plurality of layouts of the IC device corresponding to the respective values for the plurality of input variable parameter;
(c) computing a plurality of values for an output variable parameter corresponding to the plurality of input variable parameters based on the corresponding layout;
(d) determining a limiting condition on the value of the output variable parameter;
(e) determining at least one additional value for the input variable parameter based on the plurality of values for the input variable parameters, the values of the corresponding output variable parameter, and the limiting condition;
(f) repeating steps (b) through (e), with the additional value for the input variable parameter included in the plurality of input values, until a predetermined condition relating to the output variable parameter is met; and
(g) generating, using at least one of the at least one value determined in step (e) for the input variable parameter, a layout of the IC device.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
the limiting condition is dependent on the value of output variable parameter, and the determining at least one additional value for the input variable parameter comprises determining at least one additional value for the input variable parameter based on a combination of (a) proximity to the values for the an input variable parameter for which the computed output variable parameter is greater or smaller than the other computed output variable parameters and (b) uncertainty in the computed value for the output variable parameter at the value for the input variable parameter.

### Claim 3 (depends on 2)

The method of claim 2, wherein step (g) comprises, when the predetermined condition is met, selecting the value for the input variable parameter for which the computed output variable parameter is greater or smaller than the other computed output variable parameters; and
generating, using a placement-and-routing EDA tool and the selected value, a layout of the IC device.

### Claim 4 (depends on 3)

The method of claim 3, further comprising fabricating an IC device based on the generated layout.

### Claim 5 (depends on 3)

The method of claim 3, wherein determining the limiting condition includes determining the limiting condition using a cost function including the output variable parameter reduced by a quantity based on a cost that is another function of the plurality of input variable parameters based on the corresponding layout.

### Claim 6 (depends on 5)

The method of claim 5, wherein the output variable parameter is utilization, and the cost is the overflow.

### Claim 7 (depends on 6)

The method of claim 6, wherein the cost function is
Utilization−(eα·overflowH+β−y)−(eα·overflowV+β−y)
where overflowH is the overflow in horizontal direction, overflowV is the overflow in vertical direction, and α, β, and γ are constants.

### Claim 8 (depends on 1)

The method of claim 1, wherein the providing a plurality of values for an input variable parameter comprises computing the plurality of values for the input variable parameter based on another IC device of a different size.

### Claim 9 (depends on 1)

The method of claim 1, wherein the input variable parameter is size of a dimension of a voltage area (VA) in the IC device or size of a dimension of the IC device.

### Claim 10

A system, comprising:
a processor; and
computer readable media accessible by the processor and storing instructions that when executed by the processor implement a method that includes
(a) providing a plurality of values for an input variable parameter of the IC device;
(b) generating a plurality of layouts of the IC device corresponding to the respective values for the plurality of input variable parameter;
(c) computing a plurality of values for an output variable parameter corresponding to the plurality of input variable parameters based on the corresponding layout;
(d) determining a limiting condition on the value of the output variable parameter;
(e) determining at least one additional value for the input variable parameter based on the plurality of values for the input variable parameters, the values of the corresponding output variable parameter, and the limiting condition;
(f) repeating steps (b) through (e), with the additional value for the input variable parameter included in the plurality of input values until a predetermined condition relating to the output variable parameter is met; and
(g) generating, using at least one of the at least one value determined in step (e) for the input variable parameter, a layout of the IC device.

### Claim 11 (depends on 10)

The system of claim 10, wherein step (g) of the method includes:
when the predetermined condition is met, selecting the value for the input variable parameter for which the computed output variable parameter is greater or smaller than the other computed output variable parameters; and
generating, using a placement-and-routing EDA tool and the selected value, a layout of the IC device.

### Claim 12 (depends on 11)

The system of claim 11, wherein the method further comprises determining a limiting condition on the value of the output variable parameter, wherein the selecting the value for the input variable parameter comprises selecting the value for the input variable parameter for which the computed output variable parameter is greater or smaller than the other computed output variable parameters, subject to the limiting condition.

### Claim 13 (depends on 12)

The method of claim 12, wherein:
the method further comprises computing an overflow for the IC device, wherein:
the output variable parameter is utilization; and
the limiting condition is dependent on the computed overflow.

### Claim 14 (depends on 10)

The system of claim 10, further comprising an IC manufacturing system configured to receive the layout generated by the processor and fabricate an IC device based on the generated layout.

### Claim 15 (depends on 10)

The system of claim 10, wherein the input variable parameter is size of a dimension of a voltage area (VA) in the IC device or size of a dimension of the IC device.

### Claim 16 (depends on 15)

The system of claim 15, wherein the output variable parameter is utilization.

### Claim 17 (depends on 10)

The system of claim 10, wherein the determining at least one additional value for the input variable parameter comprises determining at least one additional value for the input variable parameter using a Bayesian optimization process.

### Claim 18

A method, comprising:
computing, using a first EDA tool and from a post-route layout of an electronic circuit, a first set of values for a performance parameter for the electronic circuit; and
computing a set of values for one or more electrical characteristics of the circuit by:
(a) providing a set of input values of the one or more electrical characteristics;
(b) computing, using a second EDA tool and the set of input values of the electrical characteristics, a second set of values of the performance parameter for the electronic circuit;
(c) determining a limiting condition on values of the performance parameter;
(d) comparing the second set of values of the performance parameter with the first set of values of the performance parameter, and modifying the set of input values of the electrical characteristics by a Bayesian optimization process, subject to the limiting condition;
(e) repeating steps (b) through (d) until the second set of values of the performance parameter bares a predetermined relationship with the first set of values of the performance parameter; and
(f) generating, using the set of modified input values of the electrical characteristics, a modified layout of electronic circuit.

### Claim 19 (depends on 18)

The method of claim 18, wherein the one or more electrical characteristics comprise resistance and capacitance (RC values), and wherein the performance parameter is net delay.

### Claim 20 (depends on 19)

The method of claim 19, the predetermined relationship is that a value measuring the difference between the second set of values of the performance parameter and the first set of values of the performance parameter is below a predetermined value, the method further comprising:
selecting the RC values when the value measuring the difference between the second set of values of the performance parameter and the first set of values of the performance parameter is below the predetermined value; and
using a logic synthesis EDA tool to generate a netlist at least partially based on the selected RC values.