# US 12,001,727 B2 · Techniques for managed NAND translation with embedded memory systems

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,001,727 B2
- Document ID: US12001727B2
- Status: Granted
- Kind: B2
- Application number: 17/458,781
- Filed: 2021-08-27
- Published: 2022-03-03
- Granted: 2024-06-04
- Earliest claimed: 2020-08-28
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Wanmo Wong; Brady L. Keays
- Web page: https://patentgrep.com/patent/US12001727B2

## CPC

- G06F 3/0661: {Format or protocol conversion arrangements}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0632: {by initialisation or re-initialisation of storage systems}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 12/0866: for peripheral storage systems, e.g. disk cache
- G06F 12/0888: using selective caching, e.g. bypass
- G06F 2212/1024: Latency reduction
- G06F 2212/214: Solid state disk
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7206: Reconfiguration of flash memory system
- G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Methods, systems, and devices for techniques for managed NAND translation with embedded memory systems are described. A host system may generate a first command to access a logical memory address associated with a memory system. The host system may identify a physical memory address of the memory system based on generating the first command. The host system may output to the memory system a second command and the physical memory address, where the second command may be communicated to the memory device using a protocol associated with a controller of the memory system. The memory system may then access memory cells in a memory device associated with the physical memory address based on receiving the second command and the physical memory address.

## Claims

### Claim 1

An apparatus, comprising:
a host system configured to:
generate a first command according to a first protocol, the first command to access a logical memory address associated with a memory system;
determine, after generating the first command according to the first protocol, that the memory system uses a second protocol;
identify, via a first driver, a physical memory address of the memory system based at least in part on determining that the memory system uses the second protocol; and
output, via the first driver, (i) a second command according to the second protocol and (ii) the physical memory address based at least in part on identifying the physical memory address;
output, via a second driver and based at least in part on the second command, a third command to a third driver;
output, via the third driver and based at least in part on the third command, a fourth command to the memory system, the third driver configured to communicate with the memory system according to the second protocol;
the memory system comprising:
a memory device; and
a controller coupled with the memory device and the host system, wherein the controller is configured to:
receive the fourth command and the physical memory address from the host system, wherein the physical memory address is communicated according to the second protocol associated with the controller; and
access memory cells in the memory device associated with the physical memory address based at least in part on receiving the fourth command and the physical memory address.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein outputting the second command comprises the host system being configured to:
convert the first command that uses the first protocol to the second command that uses the second protocol.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein:
the second command is converted at the first driver of the host system.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the third driver is a core driver associated with the first protocol at the host system.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein:
the host system is further configured to output, to the memory system, a set of data associated with the physical memory address using the second protocol; and
the controller is further configured to:
receive the set of data; and
store the set of data at the memory cells associated with the physical memory address based at least in part on receiving the set of data.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the controller is further configured to erase data from the memory cells based at least in part on receiving the fourth command, wherein the fourth command is an erase command.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the host system is further configured to:
enable, based at least in part on outputting the fourth command, a bus coupled with the host system and the memory system to transfer the physical memory address associated with the memory cells.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the memory system further comprises an interface coupled with the host system and the memory device.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the memory system is embedded with a circuit of the host system and the controller is a multi-media controller.

### Claim 10

A method performed by a system, comprising:
generating, at a host system, a first command according to a first protocol, the first command to access a logical memory address associated with a memory system;
determining, after generating the first command according to the first protocol, that the memory system uses a second protocol;
identifying, via a first driver at the host system, a physical memory address of the memory system based at least in part on determining that the memory system uses the second protocol;
outputting, via the first driver at the host system, (i) a second command according to the second protocol and (ii) the physical memory address of the memory system based at least in part on generating the first command;
outputting, via a second driver at the host system and based at least in part on the second command, a third command to a third driver;
outputting, via the third driver at the host system to the memory system, a fourth command to the memory system and based at least in part on the third command, the third driver configured to communicate with the memory system according to the second protocol;
receiving, at the memory system, the fourth command and the physical memory address, wherein the physical memory address is communicated according to the second protocol associated with a multi-media controller at the memory system; and
accessing, at the memory system, memory cells in a memory device associated with the physical memory address based at least in part on receiving the fourth command and the physical memory address.

### Claim 11 (depends on 10)

The method of claim 10, wherein outputting the second command comprises:
converting the first command that uses the first protocol to the second command that uses the second protocol.

### Claim 12 (depends on 10)

The method of claim 10, wherein:
the second command is converted at the first driver of the host system.

### Claim 13 (depends on 10)

The method of claim 10, wherein the third driver is a core driver associated with the first protocol at the host system.

### Claim 14 (depends on 10)

The method of claim 10, further comprising:
outputting, to the memory system, a set of data associated with the physical memory address using the second protocol;
receiving, by the memory system, the set of data; and
storing the set of data at the memory cells associated with the physical memory address based at least in part on receiving the set of data.

### Claim 15 (depends on 10)

The method of claim 10, further comprising:
erasing data from the memory cells based at least in part on receiving the fourth command, wherein the fourth command is an erase command.

### Claim 16 (depends on 10)

The method of claim 10, further comprising:
enabling, based at least in part on outputting the fourth command, a bus coupled with the host system and the memory system to transfer the physical memory address associated with the memory cells.

### Claim 17 (depends on 10)

The method of claim 10, wherein the memory system further comprises an interface coupled with the host system and the memory device.

### Claim 18 (depends on 10)

The method of claim 10, wherein the memory system is embedded with a circuit of the host system.

### Claim 19

A non-transitory computer-readable medium storing code comprising instructions, which when executed by one or more processors of a system, cause the system to:
generate, at a host system, a first command according to a first protocol, the first command to access a logical memory address associated with a memory system;
determine, after generating the first command according to the first protocol, that the memory system uses a second protocol;
identify, via a first driver at the host system, a physical memory address of the memory system based at least in part on determining that the memory system uses the second protocol;
output, via the first driver at the host system, (i) a second command according to the second protocol and (ii) the physical memory address of the memory system based at least in part on generating the first command;
output, via a second driver at the host system and based at least in part on the second command, a third command to a third driver;
output, via the third driver at the host system to the memory system, a fourth command to the memory system and based at least in part on the third command, the third driver configured to communicate with the memory system according to the second protocol;
receive, at the memory system, the fourth command and the physical memory address, wherein the physical memory address is communicated according to the second protocol associated with a multi-media controller at the memory system; and
access, at the memory system, memory cells in a memory device associated with the physical memory address based at least in part on receiving the fourth command and the physical memory address.

### Claim 20 (depends on 19)

The non-transitory computer-readable medium of claim 19, wherein causing the system to output the second command comprises instructions, when executed by the one or more processors of the system, to further cause the system to:
convert the first command that uses the first protocol to the second command that uses the second protocol.

### Claim 21 (depends on 19)

The non-transitory computer-readable medium of claim 19, wherein the second command is converted at the first driver of the host system.

### Claim 22 (depends on 19)

The non-transitory computer-readable medium of claim 19, wherein the third driver is a core driver associated with the first protocol at the host system.

### Claim 23 (depends on 19)

The non-transitory computer-readable medium of claim 19, wherein the instructions, when executed by the one or more processors of the system, further cause the system to:
output, to the memory system, a set of data associated with the physical memory address using the second protocol;
receive the set of data; and
store the set of data at the memory cells associated with the physical memory address based at least in part on receiving the set of data.

### Claim 24 (depends on 19)

The non-transitory computer-readable medium of claim 19, wherein the instructions, when executed by the one or more processors of the system, further cause the system to:
erase data from the memory cells based at least in part on receiving the fourth command, wherein the fourth command is an erase command.

### Claim 25 (depends on 19)

The non-transitory computer-readable medium of claim 19, wherein the instructions, when executed by the one or more processors of the system, further cause the system to:
enable, based at least in part on outputting the fourth command, a bus coupled with the host system and the memory system to transfer the physical memory address associated with the memory cells.

### Claim 26 (depends on 19)

The non-transitory computer-readable medium of claim 19, wherein the memory system further comprises an interface coupled with the host system and the memory device.

### Claim 27 (depends on 19)

The non-transitory computer-readable medium of claim 19, wherein the memory system is embedded with a circuit of the host system.