# US 12,001,723 B2 · Memory device

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- Number: US 12,001,723 B2
- Document ID: US12001723B2
- Status: Granted
- Kind: B2
- Application number: 17/967,909
- Filed: 2022-10-18
- Published: 2023-02-09
- Granted: 2024-06-04
- Earliest claimed: 2016-07-13
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Akio Sugahara; Yuji Nagai
- Web page: https://patentgrep.com/patent/US12001723B2

## CPC

- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/06: Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence)
- G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals}
- G11C 7/109: {Control signal input circuits}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 16/06: Auxiliary circuits, e.g. for writing into memory
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/12: Programming voltage switching circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory system includes a memory device and a memory controller. The memory device includes a memory cell array configured to store data, a data input and output interface configured to receive a command, an address, and data to be written into the memory cell array from the memory controller, and to output data read from the memory cell array to the memory controller, and a control circuit configured to control the memory cell array to perform an operation in response to receipt of a command while a first control signal is being asserted by the memory controller and receipt of an address subsequent to the command while a second control signal is being asserted by the memory controller.

## Claims

### Claim 1

A memory system comprising:
a memory device; and
a memory controller,
wherein the memory device comprises:
a memory cell array configured to store data;
a data input and output interface configured to receive a command, an address, and data to be written into the memory cell array from the memory controller, and to output data read from the memory cell array to the memory controller;
a command register configured to store a command sent from the memory controller;
an address register configured to store an address sent from the memory controller;
a transmitter connected to the data input and output interface and configured to be driven with an enable signal; and
a control circuit configured to cause the memory cell array to perform a read operation in response to receipt of a read command while a first control signal is being asserted by the memory controller and receipt of a read address subsequent to the read command while a second control signal is being asserted by the memory controller,
wherein the memory controller concurrently asserts the first control signal and the second control signal before sending the read command to cause the control circuit of the memory device to bring the enable signal to a first level and maintain the enable signal at the first level at least until after the read command is received,
wherein the first control signal comprises a signal for causing the command register to store the command,
wherein the second control signal comprises a signal for causing the address register to store the address, and
wherein, in the memory device, the enable signal is brought to the first level based on a first logical operation result, the first logical operation being a logical operation between a command and a second logical operation result, and the second logical operation result being a logical operation between the first control signal and the second control signal.

### Claim 2 (depends on 1)

The memory system according to claim 1, wherein:
the logical operation of the first logical operation result is a Reset and Set flip flop, and
the logical operation of the second logical operation result is a NAND gate.

### Claim 3 (depends on 1)

The memory system according to claim 1, wherein the transmitter outputs the data read from the memory cell array via the data input and output interface to the memory controller.

### Claim 4 (depends on 3)

The memory system according to claim 3, wherein the data read from the memory cell array are transmitted to the memory controller via the data input and output interface along with a data strobe signal.

### Claim 5 (depends on 4)

The memory system according to claim 4, wherein the memory controller toggles a third control signal while concurrently asserting the first control signal and the second control signal to cause the control circuit of the memory device to bring the enable signal to the first level.

### Claim 6 (depends on 5)

The memory system according to claim 5, wherein:
the memory device further includes:
a command register configured to store a command sent from the memory controller; and
an address register configured to store an address sent from the memory controller,
the first control signal comprises a signal for causing the command register to store a command,
the second control signal comprises a signal for causing the address register to store an address, and
the third control signal comprises a signal for causing the memory device to take a command or data therein.

### Claim 7 (depends on 1)

A memory system according to claim 1, comprising:
a memory device; and
a memory controller,
wherein the memory device comprises:
a memory cell array configured to store data;
a data input and output interface configured to receive a command, an address, and data to be written into the memory cell array from the memory controller, and to output data read from the memory cell array to the memory controller;
a transmitter connected to the data input and output interface and configured to be driven with an enable signal; and
a control circuit configured to cause the memory cell array to perform a read operation in response to receipt of a read command while a first control signal is being asserted by the memory controller and receipt of a read address subsequent to the read command while a second control signal is being asserted by the memory controller,
wherein the memory controller concurrently asserts the first control signal and the second control signal before sending the read command to cause the control circuit of the memory device to bring the enable signal to a first level and maintain the enable signal at the first level at least until after the read command is received, and
wherein the first level is different from a level of the enable signal after the read command is received.

### Claim 8 (depends on 7)

The memory system according to claim 7, wherein the control circuit performs the read operation in response to receipt of the read command and the read address subsequent thereto along with a falling edge or a rising edge of a third command signal.

### Claim 9

A memory system comprising:
a memory device; and
a memory controller,
wherein the memory device comprises:
a memory cell array configured to store data;
a data input and output interface configured to receive a command, an address, and data to be written into the memory cell array from the memory controller, and to output data read from the memory cell array to the memory controller;
a receiver connected to the data input and output interface and configured to be driven with an enable signal; and
a control circuit configured to cause the memory cell array to perform a write operation in response to receipt of a write command while a first control signal is being asserted by the memory controller, receipt of a write address subsequent to the write command while a second control signal is being asserted by the memory controller, and receipt of the data to be written into the memory cell array subsequent to the write address while neither of the first control signal and the second control signal is being asserted by the memory controller, and
wherein the memory controller concurrently asserts the first control signal and the second control signal before sending the write command to cause the control circuit of the memory device to bring the enable signal to a first level and maintain the enable signal at the first level at least until after the write command is received.

### Claim 10 (depends on 9)

The memory system according to claim 9, wherein:
the memory device further includes:
a command register configured to store a command sent from the memory controller; and
an address register configured to store an address sent from the memory controller,
the first control signal comprises a signal for causing the command register to store the command, and
the second control signal comprises a signal for causing the address register to store the address.

### Claim 11 (depends on 10)

The memory system according to claim 10, wherein, in the memory device, the enable signal is brought to the first level based on a first logical operation result, the first logical operation being a logical operation between a command and a second logical operation result, and the second logical operation result being a logical operation between the first control signal and the second control signal.

### Claim 12 (depends on 11)

The memory system according to claim 11, wherein:
the logical operation of the first logical operation result is a Reset and Set flip flop, and
the logical operation of the second logical operation result is a NAND gate.

### Claim 13 (depends on 9)

The memory system according to claim 9, wherein the receiver receives the data to be written into the memory cell array from the memory controller via the data input and output interface.

### Claim 14 (depends on 13)

The memory system according to claim 13, wherein the data to be written into the memory cell array are received from the memory controller via the data input and output interface along with a data strobe signal.

### Claim 15 (depends on 14)

The memory system according to claim 14, wherein the memory controller toggles a third control signal while concurrently asserting the first control signal and the second control signal to cause the control circuit of the memory device to bring the enable signal to the first level.

### Claim 16 (depends on 15)

The memory system according to claim 15, wherein:
the memory device further includes:
a command register configured to store a command sent from the memory controller; and
an address register configured to store an address sent from the memory controller,
the first control signal comprises a signal for causing the command register to store a command,
the second control signal comprises a signal for causing the address register to store an address, and
the third control signal comprises a signal for causing the memory device to take a command or data therein.

### Claim 17 (depends on 9)

The memory system according to claim 9, wherein the first level is different from a level of the enable signal after the write command is received.

### Claim 18 (depends on 17)

The memory system according to claim 17, wherein the control circuit performs the write operation in response to receipt of the write command and the write address subsequent thereto along with a falling edge or a rising edge of a third command signal.