# US 12,001,722 B2 · Technique for controlling stashing of data > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,001,722 B2 - Document ID: US12001722B2 - Status: Granted - Kind: B2 - Application number: 17/890,456 - Filed: 2022-08-18 - Published: 2024-02-22 - Granted: 2024-06-04 - Earliest claimed: 2022-08-18 - Assignees: Arm Limited - Applicants: Arm Limited - Inventors: Pavel Shamis; Honnappa Nagarahalli; Jamshed Jalal - Web page: https://patentgrep.com/patent/US12001722B2 ## CPC - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0635: {by changing the path, e.g. traffic rerouting, path reconfiguration} - G06F 3/0673: {Single storage device} - G06F 12/0804: with main memory updating (G06F12/0806 takes precedence) - G06F 12/0888: using selective caching, e.g. bypass - G06F 12/0811: with multilevel cache hierarchies - G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems - G06F 2212/1024: Latency reduction - G06F 2212/1056: Simplification - G06F 2212/306: In system interconnect, e.g. between two buses - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract There is provided an apparatus, method, and computer-readable medium. The apparatus comprises interconnect circuitry to couple a device to one or more processing elements and to one or more storage structures. The apparatus also comprises stashing circuitry configured to receive stashing transactions from the device, each stashing transaction comprising payload data and control data. The stashing circuitry is responsive to a given stashing transaction whose control data identifies a plurality of portions of the payload data, to perform a plurality of independent stashing decision operations, each of the plurality of independent stashing decision operations corresponding to a respective portion of the plurality of portions of payload data and comprising determining, with reference to the control data, whether to direct the respective portion to one of the one or more storage structures or whether to forward the respective portion to memory. ## Claims ### Claim 1 An apparatus comprising: interconnect circuitry to couple a device to one or more processing elements and to one or more storage structures; and stashing circuitry configured to receive stashing transactions from the device, each stashing transaction comprising payload data and control data; wherein the stashing circuitry is responsive to a given stashing transaction whose control data identifies a plurality of portions of the payload data, to perform a plurality of independent stashing decision operations, each of the plurality of independent stashing decision operations corresponding to a respective portion of the plurality of portions of payload data and comprising determining, with reference to the control data, whether to direct the respective portion to one of the one or more storage structures or whether to forward the respective portion to memory. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein: the control data of the given stashing transaction comprises portion identifying information indicating each of the plurality of portions of payload data; and the stashing circuitry is configured to identify each of the plurality of portions based on the portion identifying information. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein: the control data comprises destination identifying information indicating a target destination for one or more of the plurality of portions of payload data; and the stashing circuitry is configured, for each of the plurality of independent stashing decision operations that determines that the respective portion is to be directed to one of the one or more of storage structures, to determine, based on the destination identifying information, a particular storage structure of the one or more storage structures to which the respective portion is to be directed. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein: the target destination identifies a processing element of the one or more processing elements that is expected to process the portion of the payload data; and the stashing circuitry is configured to determine, as the particular storage structure, a storage structure of the one or more storage structures that is accessible to the processing element. ### Claim 5 (depends on 3) The apparatus of claim 3, wherein the stashing circuitry is configured to perform each of the plurality of independent stashing decision operations based on current system conditions. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the stashing circuitry is configured, for each of the plurality of independent stashing decision operations that determines that the respective portion is to be directed to one of the one or more storage structures, to determine the particular storage structure based on the current system conditions. ### Claim 7 (depends on 3) The apparatus of claim 3, wherein: the control data comprises priority information indicating a stashing priority for one or more of the plurality of portions of payload data; and the stashing circuitry is configured, when performing a respective stashing decision operation for the respective portion, to take into account any stashing priority provided for that respective portion. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the stashing circuitry is configured, for each of the plurality of portions for which the stashing priority indicates a lowest priority, to forward that portion to the memory. ### Claim 9 (depends on 7) The apparatus of claim 7, wherein the stashing circuitry is configured, when performing each of the plurality of independent stashing decision operations for which a stashing priority is indicated for the respective portion, to determine the particular storage structure based on the stashing priority. ### Claim 10 (depends on 7) The apparatus of claim 7, wherein: the target destination identifies a processing element of the one or more processing elements that is expected to process the portion of the payload data; the stashing circuitry is configured to determine, as the particular storage structure, a storage structure of the one or more storage structures that is accessible to the processing element; the one or more storage structures comprises a plurality of storage structures; the stashing priority is one of a higher priority or a lower priority; the processing element is coupled to a subset of the plurality of storage structures, each accessible to the processing element within a corresponding access time; the subset of the one or more storage structures comprises one or more shorter access time storage structures and one or more longer access time storage structures, the shorter access time storage structures having a shorter corresponding access time than the longer access time storage structures; and the stashing circuitry is configured, when performing each of the plurality of independent stashing decision operations for which a stashing priority is indicated for the respective portion, and when the stashing priority is the higher priority, to select, as the particular storage structure, one of the one or more shorter access time storage structures. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the stashing circuitry is configured, when performing each of the plurality of independent stashing decision operations for which a stashing priority is indicated for the respective portion, and when the stashing priority is the lower priority, to select, as the particular storage structure, one of the one or more longer access time storage structures. ### Claim 12 (depends on 10) The apparatus of claim 10, wherein the stashing circuitry is configured to determine a currently usable subset of storage structures comprising each of the subset of the plurality of storage structures for which a predetermined condition is met, and to select the particular storage structure from the currently usable subset of storage structures. ### Claim 13 (depends on 1) The apparatus of claim 1, wherein: the payload data comprises a header portion and a data portion; and the stashing circuitry is arranged to determine a first storage structure of the one or more storage structures accessible by a first processing element of the one or more processing elements anticipated to process the header portion, and a second storage structure of the one or more storage structures accessible by a second processing element of the one or more processing elements anticipated to process the data portion, based on the control data, to store the header portion in the first storage structure, and to store the data portion in the second storage structure. ### Claim 14 (depends on 1) The apparatus of claim 1, wherein the device is a Peripheral Component Interconnect Express (PCIe) device and the stashing transaction is a PCIe transaction layer packet. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein the control data is stored in a PCIe steering tag of the transaction layer packet. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the PCIe steering tag encodes information indicative of a stashable portion of the payload data and the stashing circuitry is configured to stash the stashable portion of the payload data in a first storage structure determined from the control data and to store each remaining bit of the payload data in a second storage structure determined from the control data. ### Claim 17 (depends on 1) The apparatus of claim 1, wherein the apparatus is a system on chip and the device is an off-chip device external to the system on chip. ### Claim 18 A method of operating an apparatus comprising interconnect circuitry to couple a device to one or more processing elements and to one or more storage structures, the method comprising: receiving stashing transactions from the device, each stashing transaction comprising payload data and control data; and performing, in response to a given stashing transaction whose control data identifies a plurality of portions of the payload data, a plurality of independent stashing decision operations, each of the plurality of independent stashing decision operations corresponding to a respective portion of the plurality of portions of payload data and comprising determining, with reference to the control data, whether to direct the respective portion to one of the one or more storage structures or whether to forward the respective portion to memory. ### Claim 19 A non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus comprising: interconnect circuitry to couple a device to one or more processing elements and to one or more storage structures; and stashing circuitry configured to receive stashing transactions from the device, each stashing transaction comprising payload data and control data; wherein the stashing circuitry is responsive to a given stashing transaction whose control data identifies a plurality of portions of the payload data, to perform a plurality of independent stashing decision operations, each of the plurality of independent stashing decision operations corresponding to a respective portion of the plurality of portions of payload data and comprising determining, with reference to the control data, whether to direct the respective portion to one of the one or more storage structures or whether to forward the respective portion to memory.