# US 12,001,713 B2 · Data transfer in port switch memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,001,713 B2 - Document ID: US12001713B2 - Status: Granted - Kind: B2 - Application number: 18/082,125 - Filed: 2022-12-15 - Published: 2023-04-13 - Granted: 2024-06-04 - Earliest claimed: 2018-09-24 - Applicants: Lodestar Licensing Group LLC - Inventors: Frank F. Ross - Web page: https://patentgrep.com/patent/US12001713B2 ## CPC - G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices} - G06F 3/0635: {by changing the path, e.g. traffic rerouting, path reconfiguration} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 3/0688: {Non-volatile semiconductor memory arrays} - G06F 11/201: {between storage system components} - G06F 12/0866: for peripheral storage systems, e.g. disk cache - G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems - G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) - G06F 13/1668: {Details of memory controller} - G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports - G11C 7/1075: {for multiport memories each having random access ports and serial ports, e.g. video RAM} - G06F 2212/1056: Simplification - G06F 2212/214: Solid state disk - G06F 2212/222: Non-volatile memory - G06F 2212/283: Plural cache memories - G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks - G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices - G11C 7/106: {Data output latches} - G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals} - G11C 7/1087: {Data input latches} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The present disclosure includes apparatuses and methods related to data transfer in memory. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein a first number of commands are executed to transfer data between the first number of memory devices and the host via the first number of ports and a second number of commands are executed to transfer data between the first number of memory device and the second number of memory device via the second number of ports. ## Claims ### Claim 1 An apparatus, comprising: a first number of memory devices coupled to a host via a first number of ports; and a second number of memory devices coupled to the first number of memory devices via a second number of ports, wherein the first number of memory devices are configured to transfer data between the first number of memory devices and the host via the first number of ports and the second number of memory devices are configured to transfer data between the first number of memory devices and the second number of memory devices via the second number of ports, wherein the first number of memory devices are configured to transfer data between the first number of memory devices and the host during a same clock cycle that the second number of memory devices are configured to transfer data between the first number of memory devices and the second number of memory devices. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the first number of memory devices are configured to receive a first number of commands from the host that include addresses to the first number of memory devices to transfer data between the first number of memory devices and the host. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the first number of memory devices are configured to execute a first number of commands by sending a status signal from a controller coupled to the first and second number of memory devices to the host. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the first number of memory devices are configured to receive a first number of commands from the host in response to a change in a ready/wait signal sent from a controller coupled to the first and second number of memory devices to the host. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the apparatus is a non-volatile dual in-line memory module (NVDIMM), the first number of memory devices are volatile memory devices, and the second number of memory devices are non-volatile memory devices. ### Claim 6 An apparatus, comprising: memory module, wherein the memory module includes a first number of memory devices and a second number of memory devices coupled to a controller, wherein the memory module is coupled to a host, and wherein the memory module is configured to: receive a first number of commands for execution on a first portion of the first number of memory devices via a first number of ports; and receive a second number of commands for execution on a second portion of the first number of memory devices on the memory module via the first number of ports wherein a multiplexor is configured to isolate the second portion of the first number of memory devices from the host in response to memory module receiving the second number of commands. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the memory module is configured to receive a third number of commands for execution on a first portion of the second number of memory devices via a second number of ports. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the first number of commands and the third number of commands are executed during a same clock cycle. ### Claim 9 (depends on 6) The apparatus of claim 6, wherein the second portion of the first number of memory devices is configured as cache for a second portion of the second number of memory devices. ### Claim 10 (depends on 6) The apparatus of claim 6, wherein the second number of commands include addresses to a second portion of the second number of memory devices. ### Claim 11 (depends on 6) The apparatus of claim 6, wherein the second portion of the first number of memory devices is configured as cache for another memory module coupled to the host. ### Claim 12 A method, comprising: receiving, from a host device, a first command via a first port of a first memory die of a memory device on a memory module, wherein the memory device comprises a first bus coupled between the first port and the host device and a second bus coupled between a second port of the first memory die and a controller of the memory module; receiving, from the controller of the memory module, a second command via a second port of a second memory die of the memory device, wherein a first port of the second memory die is coupled to the first bus of the memory device and the second port of the second memory die is coupled to the second bus of the memory device; and executing the first command at the first memory die of the first device and the second command at the second memory die of the first device, wherein first memory die and the second memory die are paired together via the first port and second port and wherein the second memory die is isolated from the host device by a multiplexor and the first port. ### Claim 13 (depends on 12) The method of claim 12, further comprising isolating the first memory die from the controller via the multiplexor and the second port. ### Claim 14 (depends on 12) The method of claim 12, wherein the first command and the second command are executed during a same clock cycle. ### Claim 15 (depends on 12) The method of claim 12, wherein executing the second command comprises transferring data from the second memory die to another device of the memory module via the controller of the memory module. ### Claim 16 (depends on 12) The method of claim 12, further comprising executing a third command to transfer data between the first memory die and the second memory die via the controller of the memory module to reconcile data in the first memory die and second memory die after executing the first command and the second command. ### Claim 17 (depends on 12) The method of claim 12, further comprising executing the first command at the first memory die of the first device while executing the second command at the second memory die of the first device.