# US 12,001,711 B2 · Determine link startup sequence (LSS) type using reference clock frequency and attribute

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- Number: US 12,001,711 B2
- Document ID: US12001711B2
- Status: Granted
- Kind: B2
- Application number: 17/875,054
- Filed: 2022-07-27
- Published: 2023-02-02
- Granted: 2024-06-04
- Earliest claimed: 2021-07-27
- Assignees: Western Digital Technologies, Inc.
- Applicants: Western Digital Technologies, Inc.
- Inventors: Rotem Sela; Shemmer Choresh
- Web page: https://patentgrep.com/patent/US12001711B2

## CPC

- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0613: {in relation to throughput}
- G06F 3/0632: {by initialisation or re-initialisation of storage systems}
- G06F 3/0634: {by changing the state or mode of one or more devices}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

The present disclosure generally relates to utilizing the host clock signal frequency to determine whether to operate in the default pulse width modulation (PWM) link startup sequence (LSS), be changed to high speed (HS) LSS by a host device capable of operating in either PWM LSS or HS LSS, or ignore the data storage device attributes of operating in PWM LSS and instead operate according to HS LSS. In so doing, the data storage device is adaptable to work with older generation UFS host devices as well as current and future generation UFS host devices.

## Claims

### Claim 1

A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, the controller configured to:
set first default link attributes to a first frequency at a first power on, wherein the first default link attributes is a pulse width modulation (PWM) link startup sequence (LSS);
receive a host reference clock signal from a host device, wherein the host reference clock signal has a second frequency and second default link attributes different from the first default link attributes, wherein the second default link attributes is a high speed (HS) LSS;
determine that the second frequency is higher than the first frequency;
ignore the first frequency;
operate at the second frequency while maintaining the first default link attributes; and
change from the first default link attributes to the second default link attributes at a second power on.

### Claim 2 (depends on 1)

The data storage device of claim 1, further comprising:
a printed circuit board (PCB);
a pin; and
a resistor.

### Claim 3 (depends on 2)

The data storage device of claim 2, wherein the resistor is not directly coupled to the host device.

### Claim 4 (depends on 2)

The data storage device of claim 2, wherein the pin is coupled to the resistor.

### Claim 5 (depends on 4)

The data storage device of claim 4, wherein the resistor is coupled to the PCB.

### Claim 6 (depends on 2)

The data storage device of claim 2, wherein the resistor is configured to either pull up or pull down to create a fixed signal, wherein the fixed signal corresponds to either a low frequency corresponding to first frequency or a high frequency corresponding to the second frequency.

### Claim 7 (depends on 1)

The data storage device of claim 1, wherein the host device is an application processor (AP).

### Claim 8 (depends on 1)

The data storage device of claim 1, wherein first frequency operates at 19.4 MHZ, 26 MHZ, 38.4 MHZ, or 52 MHz.

### Claim 9 (depends on 1)

The data storage device of claim 1, wherein the second frequency operates at 78.6 MHz or 104 MHz.

### Claim 10 (depends on 1)

The data storage device of claim 1, wherein the host device has an internal indication for whether to start in the second frequency or the first frequency.

### Claim 11

A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, the controller configured to:
set default link attributes to a first frequency at a first power on, wherein the default link attributes is a PWM LSS;
receive a host reference clock signal from a host device, wherein the host reference clock signal has a second frequency and a second link attributes different from the default link attributes;
receive instructions from the host device to change the link attributes to the second frequency;
change the default link attributes to the second link attributes;
operate as the second frequency with the second link attributes at a second power on, based on the change, wherein the second link attributes is a HS LSS.

### Claim 12 (depends on 11)

The data storage device of claim 11, wherein the host device is a 4th Generation UFS device.

### Claim 13 (depends on 11)

The data storage device of claim 11, comprising a register.

### Claim 14 (depends on 13)

The data storage device of claim 13, wherein changing the default link attributes is performed by a LSS register.

### Claim 15 (depends on 11)

The data storage device of claim 11, wherein changing the default link attributes is performed by a resistor and a pin.

### Claim 16 (depends on 11)

The data storage device of claim 11, wherein the host device is an application processor (AP), wherein the data storage device comprises a printed circuit board (PCB) and either:
a resistor and a pin; or
a register.