# US 12,001,708 B2 · In-memory associative processing for vectors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,001,708 B2 - Document ID: US12001708B2 - Status: Granted - Kind: B2 - Application number: 17/647,944 - Filed: 2022-01-13 - Published: 2023-03-02 - Granted: 2024-06-04 - Earliest claimed: 2021-08-31 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Sean S. Eilert; Ameen D. Akel; Justin Eno; Brian Hirano - Web page: https://patentgrep.com/patent/US12001708B2 ## CPC - G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices} - G06F 9/3877: {using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12)} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 9/30018: {Bit or string instructions} - G06F 9/30029: {Logical and Boolean instructions, e.g. XOR, NOT} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 15/8038: {Associative processors} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods, systems, and devices for in-memory associative processing for vectors are described. A device may perform a computational operation on a first set of contiguous bits of a first vector and a first set of contiguous bits of a second vector. The first sets of contiguous bits may be stored in a first plane of a memory die and the computational operation may be based on a truth table for the computational operation. The device may perform a second computational operation on a second set of contiguous bits of the first vector and a second set of contiguous bits of the second vector. The second sets of contiguous bits may be stored in a second plane of the memory die and the computational operation based on the truth table for the computational operation. ## Claims ### Claim 1 An apparatus, comprising: a memory die comprising a plurality of tiles each comprising a plurality of planes, wherein each plane comprises a respective array of content-addressable memory cells; and logic coupled with the memory die and configured to: perform, using associative processing, a computational operation on data representative of a first set of contiguous bits of a vector that is an operand for the computational operation, the data representative of the first set of contiguous bits stored in a first plane of a tile of the plurality of tiles; and perform, using associative processing, the computational operation on data representative of a second set of contiguous bits of the vector based at least in part on performing the computational operation on the data representative of the first set of contiguous bits, the data representative of the second set of contiguous bits stored in a second plane of the tile of the plurality of tiles. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the logic is further configured to: write data representative of a result of the computational operation on the first set of contiguous bits to the first plane of the tile; and write data representative of a result of the computational operation on the second set of contiguous bits to the second plane of the tile. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the vector comprises a plurality of elements each having a respective length, and wherein a first element of the vector comprises the first set of contiguous bits and the second set of contiguous bits. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the logic is further configured to: perform a second computational operation on data representative of a first set of contiguous bits of a second vector, the data representative of the first set of contiguous bits of the second vector stored in a first plane of a second tile; and perform the second computational operation on data representative of a second set of contiguous bits of the second vector based at least in part on performing the second computational operation on the first set of contiguous bits of the second vector, the data representative of the second set of contiguous bits of the second vector stored in a second plane of the second tile. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the logic is further configured to: perform the second computational operation on the data representative of the first set of contiguous bits of the second vector in parallel with performing the computational operation on the data representative of the first set of contiguous bits of the vector; and perform the second computational operation on the data representative of the second set of contiguous bits of the second vector in parallel with performing the computational operation on the data representative of the second set of contiguous bits of the vector. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the logic is further configured to: perform the computational operation on data representative of a first set of contiguous bits of a second vector that is an operand for the computational operation, the data representative of the first set of contiguous bits of the second vector stored in the first plane of the tile; and perform the computational operation on data representative of a second set of contiguous bits of the second vector, the data representative of the second set of contiguous bits of the second vector stored in the second plane of the tile. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the computational operation comprises an arithmetic operation, and wherein the logic is further configured to: communicate, from the first plane of the tile to the second plane of the tile, a carry bit resulting from performing the arithmetic operation on the first set of contiguous bits, wherein the arithmetic operation on the data representative of the second set of contiguous bits is based at least in part on the carry bit. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the logic is further configured to: perform, using associative processing and in parallel with performing the computational operation on the data representative of the first set of contiguous bits of the vector, a second computational operation on data representative of a first set of contiguous bits, of a second vector, stored in a second plane of a second tile. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the logic is further configured to: receive, from a host device, signaling that indicates a set of instructions indicating the vector and the computational operation; and write data representative of the vector to the first plane and the second plane according to a vector mapping scheme and based at least in part on the set of instructions. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the computational operation comprises a logic operation or an arithmetic operation. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein the memory die is configured so that a single plane per tile is operable for associative processing at a time. ### Claim 12 An apparatus, comprising: a memory die comprising a plurality of tiles each comprising a plurality of planes, wherein each plane comprises a respective array of content-addressable memory cells; and logic coupled with the memory die and configured to: perform, using associative processing, a computational operation on data representative of a first set of contiguous bits of a vector that is an operand for the computational operation, the data representative of the first set of contiguous bits stored in a first plane of a first tile of the plurality of tiles; and perform, using associative processing, the computational operation on data representative of a second set of contiguous bits of the vector based at least in part on performing the computational operation on the first set of contiguous bits, the data representative of the second set of contiguous bits stored in a first plane of a second tile of the plurality of tiles. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein the logic is further configured to: write data representative of a result of the computational operation on the data representative of the first set of contiguous bits to the first plane of the first tile; and write data representative of a result of the computational operation on the data representative of the second set of contiguous bits to the first plane of the second tile. ### Claim 14 (depends on 12) The apparatus of claim 12, wherein the vector comprises a plurality of elements each having a respective length, and wherein a first element of the vector comprises the first set of contiguous bits and the second set of contiguous bits. ### Claim 15 (depends on 12) The apparatus of claim 12, wherein the logic is further configured to: perform a second computational operation on data representative of a first set of contiguous bits of a second vector, the data representative of the first set of contiguous bits of the second vector stored in a second plane of the first tile; and perform the second computational operation on data representative of a second set of contiguous bits of the second vector based at least in part on performing the second computational operation on the data representative of the first set of contiguous bits of the second vector, the data representative of the second set of contiguous bits of the second vector stored in a second plane of the second tile. ### Claim 16 (depends on 12) The apparatus of claim 12, wherein the logic is further configured to: perform the computational operation on data representative of a first set of contiguous bits of a second vector that is an operand for the computational operation, the data representative of the first set of contiguous bits of the second vector stored in the first plane of the first tile; and perform the computational operation on data representative of a second set of contiguous bits of the second vector, the data representative of the second set of contiguous bits of the second vector stored in the first plane of the second tile. ### Claim 17 (depends on 12) The apparatus of claim 12, wherein the computational operation comprises an arithmetic operation, and wherein the logic is further configured to: communicate, from the first plane of the first tile to the first plane of the second tile, a carry bit resulting from performing the arithmetic operation on the data representative of the first set of contiguous bits, wherein the arithmetic operation on the data representative of the second set of contiguous bits is based at least in part on the carry bit. ### Claim 18 (depends on 12) The apparatus of claim 12, wherein the logic is further configured to: perform, using associative processing and in parallel with performing the computational operation on the data representative of the second set of contiguous bits of the vector, a second computational operation on data representative of a first set of contiguous bits, of a second vector, stored in a second plane of the first tile. ### Claim 19 (depends on 12) The apparatus of claim 12, wherein the logic is further configured to: perform, based at least in part on the computational operation comprising a logic operation, the logic operation on the data representative of the second set of contiguous bits in parallel with performing the logic operation on the data representative of the first set of contiguous bits. ### Claim 20 (depends on 12) The apparatus of claim 12, wherein the logic is further configured to: receive, from a host device, signaling that indicates a set of instructions indicating the vector and the computational operation; and write data representative of the vector to the first plane and a second plane according to a vector mapping scheme and based at least in part on the set of instructions. ### Claim 21 An apparatus, comprising: a memory die comprising a plurality of tiles each comprising a plurality of planes, wherein each plane comprises a respective array of content-addressable memory cells; and logic coupled with the memory die and configured to: perform, on data representative of a first set of contiguous bits of a first vector and data representative of a first set of contiguous bits of a second vector, a computational operation based at least in part on a truth table that indicates results of the computational operation for various combinations of logic values, the data representative of the first sets of contiguous bits stored in a first plane of a tile of the plurality of tiles; and perform, on data representative of a second set of contiguous bits of the first vector and data representative of a second set of contiguous bits of the second vector, the computational operation based at least in part on the truth table for the computational operation, the data representative of the second sets of contiguous bits stored in a second plane of the tile of the plurality of tiles. ### Claim 22 (depends on 21) The apparatus of claim 21, wherein the logic is further configured to: communicate, from the first plane of the tile to the second plane of the tile, a carry bit resulting from the computational operation performed on the data representative of the first sets of contiguous bits, wherein the computational operation performed on the data representative of the second sets of contiguous bits is based at least in part on the carry bit. ### Claim 23 (depends on 21) The apparatus of claim 21, wherein the logic is further configured to: perform, in parallel with performing the computational operation on the data representative of the first sets of contiguous bits, a second computational operation on data representative of a first set of contiguous bits, of a third vector, stored in a first plane of a second tile. ### Claim 24 (depends on 21) The apparatus of claim 21, wherein the logic is further configured to: receive, from a host device, signaling that indicates a set of instructions indicating the first vector, the second vector, and the computational operation; and write, based at least in part on the set of instructions, the data representative of the first sets of contiguous bits to the first plane of the tile and the data representative of the second sets of contiguous bits to the second plane of the tile. ### Claim 25 An apparatus, comprising: a memory die comprising a plurality of tiles each comprising a plurality of planes, wherein each plane comprises a respective array of content-addressable memory cells; and a logic coupled with the memory die and configured to: perform, on data representative of a first set of contiguous bits of a first vector and data representative of a first set of contiguous bits of a second vector, a computational operation based at least in part on a truth table that indicates results of the computational operation for various combinations of logic values, the data representative of the first sets of contiguous bits stored in a first plane of a first tile of the plurality of tiles; and perform, on data representative of a second set of contiguous bits of the first vector and data representative of a second set of contiguous bits of the second vector, the computational operation based at least in part on the truth table for the computational operation, the data representative of the second sets of contiguous bits stored in a first plane of a second tile of the plurality of tiles. ### Claim 26 (depends on 25) The apparatus of claim 25, wherein the logic is further configured to: communicate, from the first plane of the first tile to a second plane of the second tile, a carry bit resulting from the computational operation performed on the data representative of the first sets of contiguous bits, wherein the computational operation performed on the data representative of the second sets of contiguous bits is based at least in part on the carry bit. ### Claim 27 (depends on 25) The apparatus of claim 25, wherein the logic is further configured to: perform, in parallel with performing the computational operation on the data representative of the second sets of contiguous bits, a second computational operation on data representative of a first set of contiguous bits, of a third vector, stored in a second plane of the first tile. ### Claim 28 (depends on 25) The apparatus of claim 25, wherein the logic is further configured to: receive, from a host device, signaling that indicates a set of instructions indicating the first vector, the second vector, and the computational operation; and write, based at least in part on the set of instructions, the data representative of the first sets of contiguous bits to the first plane of the first tile and the data representative of the second sets of contiguous bits to the first plane of the second tile. ### Claim 29 A method, comprising: performing, on data representative of a first set of contiguous bits of a first vector and data representative of a first set of contiguous bits of a second vector, a computational operation based at least in part on a truth table that indicates results of the computational operation for various combinations of logic values, the data representative of the first sets of contiguous bits stored in a first plane of a first tile of a plurality of tiles; and performing, on data representative of a second set of contiguous bits of the first vector and data representative of a second set of contiguous bits of the second vector, the computational operation based at least in part on the truth table for the computational operation, the data representative of the second sets of contiguous bits stored in a first plane of a second tile of the plurality of tiles. ### Claim 30 (depends on 29) The method of claim 29, further comprising: communicating, from the first plane of the first tile to a second plane of the second tile, a carry bit resulting from the computational operation performed on the data representative of the first sets of contiguous bits, wherein the computational operation performed on the data representative of the second sets of contiguous bits is based at least in part on the carry bit. ### Claim 31 (depends on 29) The method of claim 29, further comprising: performing, in parallel with performing the computational operation on the data representative of the second sets of contiguous bits, a second computational operation on data representative of a first set of contiguous bits, of a third vector, stored in a second plane of the first tile. ### Claim 32 (depends on 29) The method of claim 29, further comprising: receiving, from a host device, signaling that indicates a set of instructions indicating the first vector, the second vector, and the computational operation; and writing, based at least in part on the set of instructions, the data representative of the first sets of contiguous bits to the first plane of the first tile and the data representative of the second sets of contiguous bits to the first plane of the second tile. ### Claim 33 A method, comprising: performing, on data representative of a first set of contiguous bits of a first vector and data representative of a first set of contiguous bits of a second vector, a computational operation based at least in part on a truth table that indicates results of the computational operation for various combinations of logic values, the data representative of the first sets of contiguous bits stored in a first plane of a memory die that comprises a plurality of tiles each comprising a plurality of planes; and performing, on data representative of a second set of contiguous bits of the first vector and data representative of a second set of contiguous bits of the second vector, the computational operation based at least in part on the truth table for the computational operation, the data representative of the second sets of contiguous bits stored in a second plane of the memory die. ### Claim 34 (depends on 33) The method of claim 33, wherein the first plane and the second plane are of a same tile, the method further comprising: communicating, from the first plane of a tile to the second plane of the tile, a carry bit resulting from the computational operation performed on the data representative of the first sets of contiguous bits, wherein the computational operation performed on the data representative of the second sets of contiguous bits is based at least in part on the carry bit. ### Claim 35 (depends on 33) The method of claim 33, wherein the first plane is of a first tile and the second plane is of a second tile, the method further comprising: communicating, from the first plane of the first tile to the second plane of the second tile, a carry bit resulting from the computational operation performed on the data representative of the first sets of contiguous bits, wherein the computational operation performed on the data representative of the second sets of contiguous bits is based at least in part on the carry bit. ### Claim 36 (depends on 33) The method of claim 33, wherein the first plane and the second plane are of a first tile, the method further comprising: performing, in parallel with performing the computational operation on the data representative of the first sets of contiguous bits, a second computational operation on data representative of a first set of contiguous bits, of a third vector, stored in a first plane of a second tile. ### Claim 37 (depends on 33) The method of claim 33, wherein the first plane is of a first tile and the second plane is of a second tile, the method further comprising: performing, in parallel with performing the computational operation on the data representative of the second sets of contiguous bits, a second computational operation on data representative of a first set of contiguous bits, of a third vector, stored in a second plane of the first tile.