# US 12,001,698 B2 · Memory system and SoC including linear address remapping logic

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- Number: US 12,001,698 B2
- Document ID: US12001698B2
- Status: Granted
- Kind: B2
- Application number: 18/105,967
- Filed: 2023-02-06
- Published: 2023-06-15
- Granted: 2024-06-04
- Earliest claimed: 2012-06-19
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Dongsik Cho
- Web page: https://patentgrep.com/patent/US12001698B2

## CPC

- G06F 3/0634: {by changing the state or mode of one or more devices}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0611: {in relation to response time}
- G06F 3/0625: {Power saving in storage systems}
- G06F 3/0638: {Organizing or formatting or addressing of data}
- G06F 3/0673: {Single storage device}
- G06F 3/0683: {Plurality of storage devices}
- G06F 12/02: Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00)
- G06F 12/0607: {Interleaved addressing}
- G06F 15/781: {On-chip cache; Off-chip memory}
- G06F 12/0646: {Configuration or reconfiguration}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G06F 2212/1016: Performance improvement
- G06F 2212/1024: Latency reduction
- G06F 2212/1028: Power efficiency
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.

## Claims

### Claim 1

A system-on-chip comprising:
a first memory port;
a second memory port;
a memory controller configured to access a first memory device through the first memory port or a second memory device through the second memory port;
a processor configured to generate memory addresses for accessing a memory region and configured to generate a control signal for selecting a linear mode and a interleave mode, and, when the memory addresses are greater than a base address, the processor generates the control signal such that the linear mode is selected; and
an address remapping logic configured to, in the linear mode, remap the memory addresses into remapped addresses based on the control signal,
wherein the memory controller is further configured to, in the linear mode, perform a first linear access operation on a first region of the memory region by accessing only the first memory device through the first memory port in response to first remapped addresses of the remapped addresses.

### Claim 2 (depends on 1)

The system-on-chip of claim 1, wherein
the memory controller is further configured to, in the linear mode, perform a second linear access operation on a second region of the memory region by accessing only the second memory device through the second memory port in response to second remapped addresses of the remapped addresses.

### Claim 3 (depends on 2)

The system-on-chip of claim 2, wherein
while the memory controller performs the first linear access operation on the first region of the memory region, the memory controller does not access the second memory device.

### Claim 4 (depends on 1)

The system-on-chip of claim 1, wherein
the memory controller is further configured to, in an interleave mode, perform an interleave access operation on a third region of the memory region by accessing both the first memory device and the second memory device through the first memory port and the second memory port.

### Claim 5 (depends on 1)

The system-on-chip of claim 1, wherein
the memory region corresponds to the first memory device and the second memory device.

### Claim 6

A system-on-chip comprising:
a first memory port;
a second memory port;
an address remapping logic configured to remap memory addresses for accessing a memory region into remapped addresses;
a processor configured to generate a control signal for selecting the memory addresses when the memory addresses are not greater than a base address and configured to generate a control signal for selecting the remapped addresses when the memory addresses are greater than a base address; and
a memory controller configured to, based on the control signal, perform a partial linear access operation on a first region of a memory region by accessing only a first memory device though the first memory port, and a partial interleave access operation on a second region of the memory region by accessing both the first memory device and a second memory devices through the first and second ports.

### Claim 7 (depends on 6)

The system-on-chip of claim 6, wherein
the processor generates the control signal based on information set in a special function register.

### Claim 8 (depends on 6)

The system-on-chip of claim 6, wherein
the processor is further configured to generate the memory addresses for accessing the memory region.

### Claim 9 (depends on 6)

The system-on-chip of claim 6, wherein
when the remapped addresses are selected by the control signal, the memory controller performs the partial linear access operation on the first region of the memory region by accessing only the first memory device though the first memory port, in response to first remapped addresses of the remapped addresses.

### Claim 10 (depends on 6)

The system-on-chip of claim 6, wherein
when the memory addresses are selected by the control signal, the memory controller performs the partial interleave access operation on the second region of the memory region by both the first and second memory devices through the first and second ports, in response to the memory addresses.

### Claim 11 (depends on 6)

The system-on-chip of claim 6, wherein
while the memory controller performs the partial linear access operation on the first region of the memory region, the memory controller is further configured to enable a clock gating or a power gating on the second memory device through the second memory port.

### Claim 12 (depends on 6)

The system-on-chip of claim 6, wherein
the memory controller is configured to perform the partial linear access operation on a third region of the memory region by accessing only the second memory device though the second memory port, in response to the remapped addresses.

### Claim 13 (depends on 12)

The system-on-chip of claim 12, wherein
while the memory controller performs the partial linear access operation on the third region of the memory region, the memory controller is further configured to enable a clock gating or a power gating on the first memory device through the first memory port.

### Claim 14

A system-on-chip comprising:
a processor configured to generate memory addresses for accessing a memory region corresponding to first and second memory devices and, when the memory addresses are greater than a base address, configured to generate a control signal to remap the memory addresses into remapped addresses;
an address remapping logic configured to remap the memory addresses into remapped addresses in response to the control signal; and
a memory controller configured to:
perform a partial linear access operation on a first region of the memory region in response to the remapped addresses in a partial linear mode, and
perform a partial interleave access operation on a second region of the memory region in response to the memory addresses, in a partial interleave mode.

### Claim 15 (depends on 14)

The system-on-chip of claim 14, further comprising:
a first memory port connected with the first memory device; and
a second memory port connected with the second memory device.

### Claim 16 (depends on 15)

The system-on-chip of claim 15, wherein
the first region of the memory region corresponds to a first area of the first memory device; and
the second region of the memory region corresponds to a second area of the first memory device and a third area of the second memory device.

### Claim 17 (depends on 14)

The system-on-chip of claim 14, wherein
the partial linear mode and the partial interleave mode are selected by the processor.