# US 12,001,693 B2 · Data storage device with noise injection

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- Number: US 12,001,693 B2
- Document ID: US12001693B2
- Status: Granted
- Kind: B2
- Application number: 17/847,068
- Filed: 2022-06-22
- Published: 2023-12-28
- Granted: 2024-06-04
- Earliest claimed: 2022-06-22
- Assignees: Western Digital Technologies, Inc.
- Applicants: Western Digital Technologies, Inc.
- Inventors: Daniel Joseph Linnen; Kirubakaran Periyannan; Ramanathan Muthiah
- Web page: https://patentgrep.com/patent/US12001693B2

## CPC

- G06F 3/0628: {making use of a particular technique}
- G11C 29/028: {with adaption or trimming of parameters}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G11C 7/02: with means for avoiding parasitic signals
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G11C 16/24: Bit-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 29/021: {in voltage or current generators}
- G11C 29/50: Marginal testing, e.g. race, voltage or current testing
- G11C 2029/5002: {Characteristic}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Noise injection procedures implemented on the die of a non-volatile memory (NVM) array are disclosed. In one example, noise is injected into data by adjusting read voltages to induce bit flips while using feedback to achieve a target amount of information degradation. In another example, random data is iteratively combined with itself to achieve a target percentage of random 1s or 0s, then the random data is combined with data read from the NVM array. In other examples, pixels are randomly zeroed out to emulate dead charge coupled device (CCD) pixels. In still other examples, the timing, voltage, and/or current values used within circuits while transferring data to/from latches or bitlines are adjusted outside their specified margins to induce bit flips to inject noise into the data. The noise-injected data may be used, for example, for dataset augmentation or for the testing of deep neural networks (DNNs).

## Claims

### Claim 1

A device formed on a die, comprising:
a non-volatile memory (NVM) array formed on the die; and
processing circuitry formed on the die and configured to:
determine a noise-reducing read voltage level that reduces an amount of noise occurring within data read from the NVM array;
set a first read voltage level to a level different from the noise-reducing read voltage level to add noise into data to be read from the NVM array, wherein the added noise is greater than an amount of noise occurring using the noise-reducing read voltage level;
read data from the NVM array using the first read voltage level set to add noise into the data to obtain a noisy version of the data;
obtain corresponding data without added noise;
compare the corresponding data with the noisy version of the data to determine an amount of noise added to the data by using the first read voltage level;
receive a value specifying an amount of noise to be added into additional data read from the NVM array;
adjust the first read voltage level to a second read voltage level based on the received value; and
read the additional data from the NVM array using the second re ad voltage level to add the specified amount of noise into the additional data read from the NVM array.

### Claim 2 (depends on 1)

The device of claim 1, wherein the processing circuitry is further configured to compare the corresponding data with the noisy version of the data by XORing the corresponding data with the noisy version of the data to obtain a count of bit differences.

### Claim 3 (depends on 1)

The device of claim 1, wherein the processing circuitry is further configured to obtain the corresponding data by being further configured to:
set the read voltage level to a third read voltage level selected to avoid adding noise; and
re-read the same data from the NVM array to obtain an alternate version of the data that has no added noise.

### Claim 4 (depends on 3)

The device of claim 3, wherein the processing circuitry is further configured to:
obtain a correct version of the data;
compare the correct version of the data to the alternate version of the data to obtain a second value that is representative of an amount of preexisting noise in the data; and
further adjust the third read voltage level based on the second value.

### Claim 5 (depends on 1)

The device of claim 1, wherein the data is neural network data, and wherein the processing circuitry is further configured to use the additional data in a neural network.

### Claim 6 (depends on 5)

The device of claim 5, wherein the processing circuitry is further configured to use the additional data in the neural network as an augmented training data set to train or test the neural network to recognize images.

### Claim 7 (depends on 1)

The device of claim 1, wherein the NVM array comprises at least one of a NAND array, a NOR array, phase-change memory (PCM) array, magneto-resistive random access memory (MRAM) arrays, a resistive random access memory (ReRAM) array, or a 3D XPoint (3DXP) array.

### Claim 8 (depends on 1)

The device of claim 1, wherein the processing circuitry is configured to determine the noise-reducing read voltage level by being further configured to:
determine a noise-minimizing read voltage level that minimizes the amount of noise occurring within the data read from the NVM array.

### Claim 9 (depends on 1)

The device of claim 1, wherein the processing circuitry is further configured to receive the value specifying the amount of noise by being further configured to:
receive a value specifying a percentage of data degradation.

### Claim 10

A method for use by a device formed on a die that includes a non-volatile memory (NVM) array, the method comprising:
determining a noise-reducing read voltage level that reduces an amount of noise occurring within data read from the NVM array;
setting a first read voltage level to a level different from the noise-reducing read voltage level to add noise into data to be read from the NVM array, wherein the added noise is greater than an amount of noise occurring using the noise-reducing read voltage level;
reading data from the NVM array using the first read voltage level set to add noise into the data to obtain a noisy version of the data;
obtaining corresponding data without added noise;
comparing the corresponding data with the noisy version of the data to determine an amount of noise added to the data by using the first read voltage level;
receiving a value specifying an amount of noise to be added into additional data read from the NVM array;
adjusting the first read voltage level to a second read voltage level based on the received value; and
reading the additional data from the NVM array using the second read voltage level to add the specified amount of noise into the additional data read from the NVM array.

### Claim 11 (depends on 10)

The method of claim 10, wherein comparing the corresponding data with the noisy version of the data comprises XORing the corresponding data with the noisy version of the data to obtain a count of bit differences.

### Claim 12 (depends on 10)

The method of claim 10, wherein obtaining the corresponding data comprises:
setting the read voltage to a level third read voltage selected to avoid adding noise; and
re-reading the same data from the NVM array to obtain an alternate version of the data that has no added noise.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
obtaining a correct version of the data;
comparing the correct version of the data to the alternate version of the data to obtain a second value that is representative of an amount of preexisting noise in the data; and
further adjusting the third read voltage level based on the second value.

### Claim 14 (depends on 12)

The method of claim 12, further comprising:
obtaining an indication of an amount of preexisting noise in the data; and
adjusting the third read voltage level based on the amount of preexisting noise.

### Claim 15 (depends on 14)

The method of claim 14, wherein the indication of the amount of preexisting noise in the data is based on a count of errors corrected via error correction coding (ECC) in the data that is re-read.

### Claim 16 (depends on 14)

The method of claim 14, wherein the indication of the amount of preexisting noise in the data is based on a count of digital-to-analog (DAC) operations performed during low-density parity-check code (LDPC) decoding of the data that is re-read.

### Claim 17 (depends on 14)

The method of claim 14, wherein the indication of the amount of preexisting noise in the data is based on an amount of change in a voltage threshold (VT) between an initial write verification read voltage level and a current read voltage level.

### Claim 18 (depends on 10)

The method of claim 10, wherein determining the noise-reducing read voltage level comprises:
determining a noise-minimizing read voltage level that minimizes the amount of noise occurring within the data read from the NVM array.

### Claim 19 (depends on 10)

The method of claim 10, wherein receiving the value specifying the amount of noise comprises receiving a value specifying a percentage of data degradation.

### Claim 20

A device formed on a die, comprising:
a memory formed on the die; and
processing circuitry formed on the die and configured to:
determine a noise-reducing read voltage level that reduces an amount of noise occurring within data read from the memory;
set a first read voltage level to a level different from the noise-reducing read voltage level to add noise into data to be read from the memory, wherein the added noise is greater than an amount of noise occurring using the noise-reducing read voltage level;
read data from the memory using the first read voltage level set to add noise into the data to obtain a noisy version of the data;
obtain corresponding data without added noise;
compare the corresponding data with the noisy version of the data to determine an amount of noise added to the data by using the first read voltage level;
receive a value specifying an amount of noise to be added into additional data read from the memory;
adjust the first read voltage level to a second read voltage level based on the received value; and
read the additional data from the NVM array using the second read voltage level to add the specified amount of noise into the additional data read from the memory.

### Claim 21 (depends on 20)

The device of claim 20, wherein the memory is a volatile memory.

### Claim 22

An apparatus for use by a device formed on a die that includes a non-volatile memory (NVM) array, the apparatus comprising:
means for determining a noise-reducing read voltage level that reduces an amount of noise occurring within data read from the NVM array;
means for setting a first read voltage level to a level different from the noise-reducing read voltage level to add noise into data to be read from the NVM array, wherein the added noise is greater than an amount of noise occurring using the noise-reducing read voltage level;
means for reading data from the NVM using the first read voltage level set to add noise into the data to obtain a noisy version of the data;
means for obtaining corresponding data without added noise;
means for comparing the corresponding data with the noisy version of the data to determine an amount of noise added to the data by using the first read voltage level;
means for receiving a value specifying an amount of noise to be added into additional data read from the NVM array;
means for adjusting the read voltage level to a second read voltage level based on the received value; and
means for reading the additional data from the NVM array using the second read voltage level to add the specified amount of noise into the additional data read from the NVM array.