# US 12,001,687 B2 · Memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,001,687 B2 - Document ID: US12001687B2 - Status: Granted - Kind: B2 - Application number: 17/942,541 - Filed: 2022-09-12 - Published: 2023-08-17 - Granted: 2024-06-04 - Earliest claimed: 2022-02-17 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Marie Takada; Masanobu Shirakawa - Web page: https://patentgrep.com/patent/US12001687B2 ## CPC - G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G06F 3/064: {Management of blocks} - G06F 3/0653: {Monitoring storage devices or systems} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/32: Timing circuits - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 2029/0411: {Online error correction} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks each including a plurality of cell units, each of the cell units including a plurality of memory cells; and a memory controller. The memory controller is configured to read second data from a second cell unit in a first block in response to first data being written in a first cell unit in the first block, and reserve refresh processing for the first block when the second data satisfies a condition. ## Claims ### Claim 1 A memory system comprising: a nonvolatile memory including a plurality of blocks each including a plurality of cell units, each of the cell units including a plurality of memory cells; and a memory controller, wherein the memory controller is configured to read second data from a second cell unit in a first block in response to first data being written in a first cell unit in the first block, and reserve refresh processing for the first block when the second data satisfies a condition. ### Claim 2 (depends on 1) The memory system according to claim 1, wherein each of the memory cells is configured to store a plurality of bits of data, the second cell unit includes a plurality of data regions corresponding to a number of bits of data stored in each of the memory cells, and the memory controller is configured to read the second data from at least one data region among the data regions of the second cell unit in response to the first data being written in the first cell unit. ### Claim 3 (depends on 2) The memory system according to claim 2, wherein the memory controller is configured to read the second data from all data regions among the data regions of the second cell unit in response to the first data being written in the first cell unit. ### Claim 4 (depends on 1) The memory system according to claim 1, wherein the second cell unit is a cell unit in which data is written first in the first block. ### Claim 5 (depends on 1) The memory system according to claim 1, wherein the first cell unit is a cell unit in which data is written last in the first block. ### Claim 6 (depends on 1) The memory system according to claim 1, wherein the memory controller is configured to write data written in the first block in a second block in the refresh processing for the first block. ### Claim 7 (depends on 1) The memory system according to claim 1, wherein the memory controller is configured to overwrite a part of data written in the first block over the first block in the refresh processing for the first block. ### Claim 8 (depends on 1) The memory system according to claim 1, wherein the condition includes a condition that a number of fail bits included in the second data is equal to or larger than a threshold. ### Claim 9 (depends on 1) The memory system according to claim 1, wherein the memory controller is configured to calculate a first shift amount concerning a read voltage applied to a third cell unit based on third data read from the third cell unit in the first block, in read processing from a fourth cell unit in the first block, calculate, based on the first shift amount, a second shift amount concerning a read voltage applied to the fourth cell unit, and read fourth data from the fourth cell unit based on the second shift amount. ### Claim 10 (depends on 9) The memory system according to claim 9, wherein the memory controller is configured to, when the second data satisfies the condition, calculate, based on the second data, a third shift amount concerning a read voltage applied to the second cell unit, and when failing in correction of a fail bit included in the fourth data in read processing from the fourth cell unit, calculate, based on the third shift amount, a fourth shift amount concerning a read voltage applied to the fourth cell unit, and read fifth data from the fourth cell unit based on the fourth shift amount. ### Claim 11 (depends on 10) The memory system according to claim 10, wherein the memory controller is configured to, when failing in correction of a fail bit included in the fifth data in read processing from the fourth cell unit, calculate, based on the first shift amount and the third shift amount, a fifth shift amount concerning a read voltage applied to the fourth cell unit, and read sixth data from the fourth cell unit based on the fifth shift amount. ### Claim 12 (depends on 10) The memory system according to claim 10, wherein the memory controller is configured to calculate the fourth shift amount and read the fifth data when writing order of the fourth cell unit in the first block is between the second cell unit and the third cell unit. ### Claim 13 (depends on 9) The memory system according to claim 9, wherein the memory controller is configured to, when the second data satisfies the condition, read sixth data from the first cell unit based on the first shift amount, calculate a sixth shift amount concerning a read voltage applied to the first cell unit based on the sixth data, and when failing in correction of a fail bit included in the fourth data in read processing from the fourth cell unit, calculate, based on the sixth shift amount, a seventh shift amount concerning a read voltage applied to the fourth cell unit, and read seventh data from the fourth cell unit based on the seventh shift amount. ### Claim 14 (depends on 13) The memory system according to claim 13, wherein the memory controller is configured to, when failing in correction of a fail bit included in the seventh data in read processing from the fourth cell unit, calculate, based on the first shift amount and the sixth shift amount, an eighth shift amount concerning a read voltage applied to the fourth cell unit, and read eighth data from the fourth cell unit based on the eighth shift amount. ### Claim 15 (depends on 13) The memory system according to claim 13, wherein the memory controller is configured to calculate the seventh shift amount and read the seventh data when writing order of the fourth cell unit in the first block is between the first cell unit and the third cell unit. ### Claim 16 (depends on 1) The memory system according to claim 1, wherein each of the blocks is a data erasing unit.