# US 12,001,683 B2 · Memory device, memory system including the same, and operating method of the memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,001,683 B2 - Document ID: US12001683B2 - Status: Granted - Kind: B2 - Application number: 18/087,464 - Filed: 2022-12-22 - Published: 2023-06-29 - Granted: 2024-06-04 - Earliest claimed: 2021-12-28 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Heeyeon Tak; Hyunseon Park; Heehyun Nam; Sumin Ahn; Wansoo Choi - Web page: https://patentgrep.com/patent/US12001683B2 ## CPC - G06F 3/0613: {in relation to throughput} - G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers} - G06F 3/0656: {Data buffering arrangements} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G11C 7/106: {Data output latches} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 2207/2245: Memory devices with an internal cache buffer - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory system includes a memory device including a memory cell array, a first latch, a plurality of program latches, and a second latch and a memory controller configured to provide a command to the memory device. The memory device may sense first data from a first region of the memory cell array, store the sensed first data in the first latch, transfer the sensed first data to the second latch, output the first data from the second latch to the memory controller, and transfer the first data from the second latch to a first program latch of the plurality of program latches, in response to a first read command. ## Claims ### Claim 1 A memory system comprising: a memory device comprising: a memory cell array connected to a plurality of bit lines; a first latch configured to sense data stored in the memory cell array; a plurality of program latches configured to store data which is to be programmed in the memory cell array, or data which determines a voltage level pre-charged in the plurality of bit lines in performing a program operation; and a second latch configured to receive data which is to be programmed in the memory cell array, or output data sensed from the memory cell array; and a memory controller configured to provide a command to the memory device, wherein the memory device is configured to: sense first data from a first region of the memory cell array, store the first data in the first latch, transfer the first data from the first latch to the second latch, output the first data from the second latch to the memory controller, and in response to a first read command, transfer the first data from the second latch to a first program latch of the plurality of program latches. ### Claim 2 (depends on 1) The memory system of claim 1, wherein the memory controller is connected to the memory device through a pin configured to indicate a ready state or a busy state of the memory device, and wherein the pin is further configured to represent the busy state while the first data is being sensed and represent the busy state while the first data is being transferred from the second latch to the first program latch. ### Claim 3 (depends on 1) The memory system of claim 1, wherein the memory controller is further configured to, based on the first data of the first region being stored in the first program latch, output a second read command to the memory device, and wherein the second read command indicates an output of data stored in the first program latch. ### Claim 4 (depends on 3) The memory system of claim 3, wherein the memory device is further configured to: transfer the first data stored in the first program latch to the second latch, and in response to the second read command, output the first data transferred to the second latch to the memory controller. ### Claim 5 (depends on 4) The memory system of claim 4, wherein the memory controller is connected to the memory device through a pin configured to indicate a ready state or a busy state of the memory device, and wherein the pin is configured to indicate the busy state while the first data is being transferred from the first program latch to the second latch. ### Claim 6 (depends on 1) The memory system of claim 1, wherein the memory controller is further configured to perform an error correction operation on the first data and store error correction information indicating whether correction was necessary. ### Claim 7 (depends on 6) The memory system of claim 6, wherein the memory controller comprises a read buffer configured to store data corresponding to a read command, wherein the memory controller is further configured to, based on the correction of an error not being necessary, omit a second error correction operation on the first data received from the memory device and store the first data in the read buffer, and wherein the first data is received from the memory device according to a third read command corresponding to the first region. ### Claim 8 (depends on 6) The memory system of claim 6, wherein the memory controller is further configured to store a latch table including identification numbers of the plurality of program latches, physical addresses corresponding to data stored in the plurality of program latches, and the error correction information with respect to the data stored in the plurality of program latches. ### Claim 9 (depends on 1) The memory system of claim 1, wherein the memory controller is further configured to select the first program latch from among the plurality of program latches based on a cache algorithm. ### Claim 10 (depends on 1) The memory system of claim 1, wherein the plurality of program latches comprises an upper bit latch configured to store an upper bit which is to be stored in the memory cell array and a lower bit latch configured to store a lower bit which is to be stored in the memory cell array. ### Claim 11 An operating method of a memory system comprising a memory device comprising a memory cell array and a plurality of latches, and a memory controller controlling the memory device, the operating method comprising: selecting, by the memory controller, a first latch from among the plurality of latches; providing, by the memory controller, the memory device with a first physical address and a first read command comprising identification information about the first latch; providing, by the memory device, the memory controller with data sensed from a region corresponding to the first physical address in the memory cell array in response to the first read command; and storing, by the memory device, the data in the first latch. ### Claim 12 (depends on 11) The operating method of claim 11, wherein the providing the memory controller with the data sensed from the region corresponding to the first physical address comprises: sensing the data from the region corresponding to the first physical address by using a second latch of the plurality of latches; transferring the data sensed by the second latch to a third latch of the plurality of latches; and providing the memory controller with the data transferred to the third latch. ### Claim 13 (depends on 11) The operating method of claim 11, further comprising: providing, by the memory controller, the memory device with the first physical address and a second read command comprising information about the first latch; and providing, by the memory device, the memory controller with data stored in the first latch, in response to the second read command. ### Claim 14 (depends on 11) The operating method of claim 11, wherein the selecting the first latch from among the plurality of latches comprises selecting the first latch from among the plurality of latches by using a cache algorithm. ### Claim 15 (depends on 11) The operating method of claim 11, further comprising performing, by the memory controller, an error correction operation on the data received from the memory device and storing error correction information indicating whether correction was necessary. ### Claim 16 (depends on 15) The operating method of claim 15, further comprising: providing, by the memory controller, the memory device with the first physical address and a third read command including information about the first latch; and providing, by the memory device, the memory controller with data stored in the first latch, in response to the third read command, wherein the memory controller is configured to omit an error correction of data received based on the third read command. ### Claim 17 A memory device comprising: a memory cell array connected to a plurality of bit lines; a first latch configured to sense data stored in the memory cell array; a second latch configured to store data which is to be programmed in the memory cell array, or data determining a voltage level pre-charged in the plurality of bit lines in performing a program operation; and a third latch configured to receive data which is to be programmed in the memory cell array, or output data sensed from the memory cell array, wherein, in response to a first read command corresponding to a first region of the memory cell array, the first latch is configured to sense first data from the first region and transfer the first data to the third latch, and the third latch is configured to output the first data to a memory controller and transfer the first data to the second latch. ### Claim 18 (depends on 17) The memory device of claim 17, further comprising a pin configured to indicate a ready state or a busy state of the memory device, wherein the pin is configured to indicate the busy state while the first latch is sensing the first data and represent the busy state while the first data is being transferred to the second latch. ### Claim 19 (depends on 17) The memory device of claim 17, wherein, in response to a second read command corresponding to the first region, the second latch is configured to transfer the first data to the third latch, and the third latch is configured to output the first data to the memory controller. ### Claim 20 (depends on 19) The memory device of claim 19, further comprising a pin configured to indicate a ready state or a busy state of the memory device, wherein the pin is configured to represent the busy state while the second latch is transferring the first data to the third latch.