# US 12,001,680 B2 · Utilizing last successful read voltage level in memory access operations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,001,680 B2 - Document ID: US12001680B2 - Status: Granted - Kind: B2 - Application number: 17/894,540 - Filed: 2022-08-24 - Published: 2024-02-29 - Granted: 2024-06-04 - Earliest claimed: 2022-08-24 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Kyungjin Kim - Web page: https://patentgrep.com/patent/US12001680B2 ## CPC - G06F 3/0611: {in relation to response time} - G11C 29/021: {in voltage or current generators} - G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 29/028: {with adaption or trimming of parameters} - G11C 7/04: with means for avoiding disturbances due to temperature effects - G11C 29/42: using error correcting codes [ECC] or parity check - G11C 2029/0411: {Online error correction} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An example method of performing read operation with respect to a memory device comprises: receiving a request to perform a read operation with respect to a memory page of a memory device; identifying a block family associated with a block comprising the memory page; determining a block family-based read voltage level associated with the block family; performing, using the block family-based read voltage level, a read operation with respect to the memory page; determining, by performing an error correction operation with respect to the memory page, a new read voltage level associated with the block family; and associating, by a last successful read voltage level memory data structure, the new read voltage level as a last the successful read voltage level with the block family. ## Claims ### Claim 1 A method, comprising: responsive to receiving a read error associated with a read operation performed on a memory page of a memory device, determining, by performing an error correction operation, a new read voltage level associated with a block family of the memory page of the memory device; storing the new read voltage level as a last successful read voltage level in a record of a last successful read voltage level memory data structure associated with the block family; responsive to receiving a request to perform a subsequent read operation with respect to the memory page, retrieving the last successful read voltage level from the record of the last successful read voltage level memory data structure associated with the block family of the memory page; and performing, using the retrieved last successful read voltage level, the subsequent read operation with respect to the memory page. ### Claim 2 (depends on 1) The method of claim 1, further comprising: responsive to receiving a subsequent request to perform a subsequent read operation with respect to the memory page, retrieving the last successful read voltage level from the last successful read voltage level memory data structure; and performing, using the last successful read voltage level, a subsequent read operation with respect to the memory page. ### Claim 3 (depends on 1) The method of claim 1, wherein the read operation is performed using a block family-based read voltage level associated with a block family, wherein the block family is associated with a block comprising the memory page, and wherein the block family-based read voltage level is determined using a block family memory data structure comprising a plurality of records, each record mapping an identifier of a block family to a time-after-programming (TAP) bin. ### Claim 4 (depends on 3) The method of claim 3, wherein the TAP bin is associated with a plurality of voltage offsets, each voltage offset of the plurality of voltage offsets associated with a corresponding logical programming level of a plurality of logical programming levels. ### Claim 5 (depends on 1) The method of claim 1, wherein the successful read voltage level data structure comprises a plurality of records, wherein each record of the plurality of records associates a block family of a plurality of block families of the memory device with a plurality of voltage offsets, each voltage offset of the plurality of voltage offsets associated with a corresponding logical programming level of a plurality of logical programming levels. ### Claim 6 (depends on 1) The method of claim 1, wherein the block family comprises a plurality of blocks that have been programmed within a specified time window and a specified temperature window. ### Claim 7 (depends on 1) The method of claim 1, wherein identifying the block family associated with the block comprising the memory page is performed using a block family data structure comprising a plurality of records, each record mapping an identifier of a block family to a corresponding list of blocks comprised by the block family. ### Claim 8 A system comprising: a memory device; a processing device, operatively coupled to the memory device, the processing device to perform operations comprising: responsive to receiving a read error associated with a read operation performed on respect to a memory page of the memory device, determining, by performing an error correction operation, a new read voltage level associated with a block family of the memory page of the memory device; storing the new read voltage level as a last successful read voltage level in a record of a last successful read voltage level memory data structure associated with the block family; responsive to receiving a request to perform a subsequent read operation with respect to the memory page, retrieving the last successful read voltage level from the record of the last successful read voltage level memory data structure associated with the block family of the memory page; and performing, using the retrieved last successful read voltage level, the subsequent read operation with respect to the memory page. ### Claim 9 (depends on 8) The system of claim 8, wherein the operations further comprise: responsive to receiving a subsequent request to perform a subsequent read operation with respect to the memory page, retrieving the last successful read voltage level from the last successful read voltage level memory data structure; and performing, using the last successful read voltage level, a subsequent read operation with respect to the memory page. ### Claim 10 (depends on 8) The system of claim 8, wherein the read operation is performed using a block family-based read voltage level associated with a block family, wherein the block family is associated with a block comprising the memory page, and wherein the block family-based read voltage level is determined using a block family memory data structure comprising a plurality of records, each record mapping an identifier of a block family to a time-after-programming (TAP) bin. ### Claim 11 (depends on 10) The system of claim 10, wherein the TAP bin is associated with a plurality of voltage offsets, each voltage offset of the plurality of voltage offsets associated with a corresponding logical programming level of a plurality of logical programming levels. ### Claim 12 (depends on 8) The system of claim 8, wherein the successful read voltage level data structure comprises a plurality of records, wherein each record of the plurality of records associates a block family of a plurality of block families of the memory device with a plurality of voltage offsets, each voltage offset of the plurality of voltage offsets associated with a corresponding logical programming level of a plurality of logical programming levels. ### Claim 13 (depends on 8) The system of claim 8, wherein the block family comprises a plurality of blocks that have been programmed within a specified time window and a specified temperature window. ### Claim 14 (depends on 8) The system of claim 8, wherein identifying the block family associated with the block comprising the memory page is performed using a block family data structure comprising a plurality of records, each record mapping an identifier of a block family to a corresponding list of blocks comprised by the block family. ### Claim 15 A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: responsive to receiving a read error associated with a read operation performed on a memory page of a memory device, determining, by performing an error correction operation, a new read voltage level associated with a block family of the memory page; storing the new read voltage level as a last successful read voltage level in a record of a last successful read voltage level memory data structure associated with the block family; responsive to receiving a request to perform a subsequent read operation with respect to the memory page, retrieving the last successful read voltage level from the record of the last successful read voltage level memory data structure associated with the block family of the memory page; and performing, using the retrieved last successful read voltage level, the subsequent read operation with respect to the memory page. ### Claim 16 (depends on 15) The non-transitory computer-readable storage medium of claim 15, further comprising: responsive to receiving a subsequent request to perform a subsequent read operation with respect to the memory page, retrieving the last successful read voltage level from the last successful read voltage level memory data structure; and performing, using the last successful read voltage level, a subsequent read operation with respect to the memory page. ### Claim 17 (depends on 15) The non-transitory computer-readable storage medium of claim 15, wherein the read operation is performed using a block family-based read voltage level associated with a block family, wherein the block family is associated with a block comprising the memory page, and wherein the block family-based read voltage level is determined using a block family memory data structure comprising a plurality of records, each record mapping an identifier of a block family to a time-after-programming (TAP) bin. ### Claim 18 (depends on 15) The non-transitory computer-readable storage medium of claim 15, wherein the successful read voltage level data structure comprises a plurality of records, wherein each record of the plurality of records associates a block family of a plurality of block families of the memory device with a plurality of voltage offsets, each voltage offset of the plurality of voltage offsets associated with a corresponding logical programming level of a plurality of logical programming levels. ### Claim 19 (depends on 15) The non-transitory computer-readable storage medium of claim 15, wherein the block family comprises a plurality of blocks that have been programmed within a specified time window and a specified temperature window. ### Claim 20 (depends on 15) The non-transitory computer-readable storage medium of claim 15, wherein identifying the block family associated with the block comprising the memory page is performed using a block family data structure comprising a plurality of records, each record mapping an identifier of a block family to a corresponding list of blocks comprised by the block family.