# US 12,001,560 B2 · Method and system for avoiding boot failure from platform firmware resilience execution

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- Number: US 12,001,560 B2
- Document ID: US12001560B2
- Status: Granted
- Kind: B2
- Application number: 17/513,548
- Filed: 2021-10-28
- Published: 2023-05-04
- Granted: 2024-06-04
- Earliest claimed: 2021-10-28
- Assignees: Quanta Computer Inc.
- Applicants: Quanta Computer Inc.
- Inventors: Tzu-Heng Wen; Yen-Ping Tung; Wei-Hung Lin
- Web page: https://patentgrep.com/patent/US12001560B2

## CPC

- G06F 21/572: {Secure firmware programming, e.g. of basic input output system [BIOS]}
- G06F 21/575: {Secure boot}
- G06F 3/0622: {in relation to access}
- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 21/76: in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
- H04L 9/3247: {involving digital signatures}
- G06F 9/4416: {Network booting; Remote initial program loading [RIPL]}
- G06F 2221/033: Test or assess software
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A method and system to ensure correct firmware image execution in a computer system. The computer system has a processor executing a basic input/output system (BIOS) and a baseboard management controller (BMC). A first flash memory device is coupled to the processor storing a BIOS firmware image and a project name. A second flash memory device is coupled to the BMC storing a BMC firmware image and the project name. A programmable logic device is coupled to the first and second flash memory devices. The programmable logic device including a non-volatile memory storing a project name. The programmable logic device is configured to execute a Platform Firmware Resilience routine to compare the project name of the BIOS firmware image and the project name of the BMC firmware image with the stored project name before starting the BMC or executing the BIOS firmware image by the processor.

## Claims

### Claim 1

A system to ensure execution of a correct firmware image in a computer system, the system comprising:
a flash memory for storing a firmware image including a project name;
a processor executing the firmware image; and
a programmable logic device executing a Platform Firmware Resilience routine separate from the firmware image, the routine monitoring and filtering malicious traffic on a system bus coupled to the processor, the programmable logic device including a non-volatile memory with an active area storing a project name, wherein the programmable logic device is configured to compare the project name of the firmware image and the project name stored in the non-volatile memory, and prevent access by the processor to the firmware image on the flash memory if the project names do not match, and wherein the programmable logic device is further configured to receive a request for a firmware update after booting of the processor, compare a project name of a firmware update with the stored project name, and prevent loading of the firmware update if the project name of the firmware update and the stored project name do not match while allowing the processor to continue to function.

### Claim 2 (depends on 1)

The system of claim 1, further comprising a baseboard management controller (BMC), wherein the firmware image is a BMC firmware image.

### Claim 3 (depends on 1)

The system of claim 1, wherein the programmable logic device is a field programmable gate array (FPGA).

### Claim 4 (depends on 1)

The system of claim 1, wherein the firmware image is a basic input/output system (BIOS) firmware image.

### Claim 5 (depends on 1)

The system of claim 1, wherein the programmable logic device is further configured to authenticate a signature of the firmware image with a stored public key.

### Claim 6 (depends on 1)

The system of claim 1, wherein the project name of the firmware image is stored in a field of a Platform Firmware Manifest data structure stored in the flash memory.

### Claim 7 (depends on 1)

The system of claim 1, wherein the project name is stored in the non-volatile memory when the computer system is initially provisioned.

### Claim 8 (depends on 1)

The system of claim 1, further comprising a multiplexer controlled by the programmable logic device is coupled between the processor and the flash memory, wherein the programmable logic device prevents access by the processor to the firmware image on the flash memory by controlling the multiplexer.

### Claim 9

A method of ensuring correct firmware images in a computer system, the method comprising:
storing a project name in a memory of a programmable logic device executing a Platform Firmware Resilience routine separate from the firmware image, the routine monitoring and filtering malicious traffic on a system bus coupled to a processor;
comparing the stored project name with a project name of a firmware image executable by the processor;
preventing access by the processor to the firmware image if the stored project name does not match the project name of the firmware image;
receiving a request for a firmware update after booting of the processor;
comparing a project name of a firmware update with the stored project name; and
preventing loading of the firmware update if the project name of the firmware update and the stored project name do not match while allowing the processor to continue to function.

### Claim 10 (depends on 9)

The method of claim 9, wherein the firmware image is a BMC firmware image executable by a baseboard management controller.

### Claim 11 (depends on 9)

The method of claim 9, wherein the programmable logic device is a field programmable gate array (FPGA).

### Claim 12 (depends on 9)

The method of claim 9, wherein the firmware image is a basic input/output system (BIOS) firmware image.

### Claim 13 (depends on 9)

The method of claim 9, further comprising authenticating a signature of the firmware image with a stored public key via the programmable logic device.

### Claim 14 (depends on 9)

The method of claim 9, wherein the project name of the firmware image is stored in a field of a Platform Firmware Manifest data structure.

### Claim 15 (depends on 9)

The method of claim 9, further comprising storing the project name during a provisioning process of the computer system.

### Claim 16 (depends on 9)

The method of claim 9, wherein a multiplexer controlled by the programmable logic device is coupled between the processor and a flash memory storing the firmware image, wherein the programmable logic device prevents access by the processor to the firmware image on the flash memory by controlling the multiplexer.

### Claim 17

A computer system comprising:
a processor executing a basic input/output system (BIOS);
a baseboard management controller (BMC);
a first flash memory device coupled to the processor, the first flash memory storing a BIOS firmware image and a project name of the BIOS firmware image;
a second flash memory device coupled to the BMC, the second flash memory storing a BMC firmware image and a project name of the BMC firmware image; and
a programmable logic device coupled to the first and second flash memory devices, the programmable logic device including a non-volatile memory storing a project name and configured to execute a Platform Firmware Resilience routine separate from the BIOS firmware image and the BIOS firmware image, the routine monitoring and filtering malicious traffic on a system bus coupled to the processor and the BMC, to compare the project name associated with the BIOS firmware image and the project name associated with the BMC firmware image with the project name stored in the non-volatile memory before starting the BMC or executing the BIOS firmware image by the processor, and wherein the programmable logic device is further configured to receive a request for a firmware update after booting of the processor, compare a project name of a firmware update with the stored project name, and prevent loading of the firmware update if the project name of the firmware update and the stored project name do not match while allowing the processor to continue to function.