# US 12,001,547 B2 · Method, system and apparatus for detecting malicious modifications to semiconductor devices

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- Number: US 12,001,547 B2
- Document ID: US12001547B2
- Status: Granted
- Kind: B2
- Application number: 17/529,640
- Filed: 2021-11-18
- Published: 2023-05-18
- Granted: 2024-06-04
- Earliest claimed: 2021-11-18
- Assignees: Rocksavage Technology, Inc.
- Applicants: Rocksavage Technology, Inc.
- Inventors: Thomas Warren Savage
- Web page: https://patentgrep.com/patent/US12001547B2

## CPC

- G06F 21/55: Detecting local intrusion or implementing counter-measures
- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G06F 30/333: Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
- G06F 7/584: {using finite field arithmetic, e.g. using a linear feedback shift register}
- G06F 2111/04: Constraint-based CAD
- G06F 2221/034: Test or assess a computer or a system
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A computer-implemented method, and system, for detecting modification of a semiconductor device includes generating and applying an exhaustive first set of patterns to a netlist golden model of a golden device. The exhaustive first set of patterns is developed by a pseudorandom number generator. Applying the patterns to stimulate the device produces a first response serial bit stream in relation to logical composition of the golden model. A signature analyzer compresses the total output to provide a first cyclic redundancy code or answer. The same exhaustive set of patterns can be provided to stimulate the model of an unknown device. The unknown device is shown to be identical to the golden device if its answer matches that of the golden device and modified if its answer does not match that of the golden device.

## Claims

### Claim 1

A detecting method capable of detecting a modification in a semiconductor device, said method comprising:
first applying, by an algorithm executed in a computer simulation, an exhaustive first set of patterns to inputs of a model of an original semiconductor device, said exhaustive first set of patterns developed by a pseudorandom number generator initialized with seed values;
first producing, by said computer simulation, a first set of response patterns from outputs of said model;
first compressing, by a signature analyzer, said first set of response patterns to provide to a first cyclic redundancy code in relation to said first applying;
second applying, by by a hardware implementation of said algorithm and said pseudorandom number generator, an identical exhaustive set of patterns to inputs of a manufactured physical device of said design;
second producing, by said hardware implementation, a second set of response patterns from outputs of said physical device;
second compressing, by a signature analyzer in said hardware implementation, said response patterns to provide to a second cyclic redundancy check code in relation to said second applying;
comparing, by said hardware implementation, said second cyclic redundancy check code to said first cyclic redundancy check code to determine one of identity or non-identity of said second cyclic redundancy check code to said first cyclic redundancy check code; and
categorizing, by said hardware implementation, said physical device in relation to said comparing, said categorizing further comprising:
failing, if said comparing determines non-identity, of said physical device; and
passing, if said comparing determines identity, of said physical device.

### Claim 2 (depends on 1)

A detecting method of claim 1, said method further comprising:
first preparing the original semiconductor design for simulation, said first preparing further comprising:
first imposing a set of detection testing constraints in said design.

### Claim 3 (depends on 2)

A detecting method of claim 2, said method further comprising:
said first imposing said set of design constraints in said original semiconductor design further comprising:
placing flip-flops in scannable condition;
placing latches in one of scannable condition and transparent condition;
fencing non-digital logic to provide a deterministic response to each applied pattern;
fencing non-digital memory to provide a definite response to each applied pattern;
sizing logic cones to not exceed length of pseudorandom number generators used for automatically generating patterns; and
configuring digital logic to reset to a consistent state prior to pattern application.

### Claim 4 (depends on 2)

A detecting method of claim 2, said method further comprising:
said first imposing said set of design constraints in original semiconductor design further comprising:
first insertion into the netlist for manufacturing testing by the following:
performing scan insertion into a final netlist with all flip-flops organized into n-number scan chains of maximal m-length, wherein n and m relate to design characteristics of said design; and
fencing non-digital elements to produce, from said netlist under test, repeatable responses when patterns are applied.

### Claim 5 (depends on 1)

A detecting method of claim 1, said method further comprising:
first generating a hardware design model of a test system configured to perform steps of said detecting method; and
second simulating, said system to establish the identity of an original semiconductor device design.

### Claim 6 (depends on 5)

A detecting method of claim 5, said method further comprising:
said first generating further comprising said test bench capable of accelerating the simulating of said detecting method by generating a plurality of testbenches executable by cloud servers.

### Claim 7 (depends on 5)

A detecting method of claim 5, said method further comprising:
said first generating a test bench system to perform steps of said detecting method as follows:
connecting to each of said n-number scan chain inputs of the original device, an output pin of a corresponding pseudorandom number generator of the test bench system;
connecting to each of said n-number scan chain outputs of the original device, an input pin of a corresponding signature analyzer of the test bench system;
connecting each primary input pin of said device to a corresponding primary output pin of the test bench system; and
connecting to each primary output pin of said device to a primary input pin of the test bench.

### Claim 8

A detecting method capable of detecting modification in a semiconductor device, said method comprising:
first generating a test bench system to perform steps of said detecting method;
executing, by said test bench system, an exhaustive design under test (DUT) algorithm;
first extracting, in relation to said executing, a full set of input patterns (input vectors) applied to the netlist golden model under test on said test bench system;
second extracting, in relation to said executing, a full set of output patterns (output vectors) generated by applying the full set of input patterns (input vectors) to check functioning of the netlist golden model under test on said test bench system;
performing, by a signature analyzer, compression to provide cyclic redundancy code (CRC) in relation to said first extracting and said second extracting;
categorizing, by a processor, in relation to said first applying and said second applying, said physical integrated circuit in relation to the netlist golden model, said categorizing further comprising one of:
failing, if said categorizing determines non-identity, said semiconductor device; and
passing, if said categorizing determines identity, said semiconductor device.

### Claim 9 (depends on 8)

A computer-implemented detecting method of claim 8, further comprising:
said executing, by a test bench system, an exhaustive design under test (DUT) algorithm, said algorithm consisting of the following:
initializing each pseudorandom number generator with seed values;
initializing each signature analyzer to zero;
resetting design under test (DUT);
looping for 65536 cycles;
simultaneously scanning in new pseudorandom number generator pattern for (m) clocks and scanning out result of previous pattern;
executing one non-scan clock; and
ending loop.

### Claim 10 (depends on 1)

A computer-implemented detecting method of claim 1, further comprising:
first generating a test bench system to perform steps of said detecting method;
executing, by said test bench system, an exhaustive design under test (DUT) algorithm, said algorithm consisting of the following:
initializing each pseudorandom number generator with seed values;
initializing each signature analyzer to zero;
resetting design under test (DUT);
looping for 65536 cycles;
simultaneously scanning in new pseudorandom number generator pattern for (m) clocks and scanning out result of previous pattern;
executing one non-scan clock; and
ending loop.

### Claim 11 (depends on 1)

A detection system capable of detecting a modification in a manufactured physical device, said detection system comprising:
an application to automatically generate the hardware design of the detecting method of claim 1.

### Claim 12 (depends on 1)

A hardware implementation of said design comprising:
executing, autonomously without a processor the method of claim 1.

### Claim 13 (depends on 1)

An automated design system for automated design of a semiconductor device, said automated design system comprising:
an application configured to perform the detecting method of claim 1.

### Claim 14 (depends on 1)

A computer-implemented manufacturing method capable of providing an authenticated semiconductor device, said manufacturing method comprising:
producing, by a processor, said semiconductor device comprising an integrated circuit (IC) from an IC manufacturing file generated by an electronic design automation (EDA) tool in relation to an IC design file;
providing, by a processor, said IC design file by performing the computer-implemented detecting method of claim 1.

### Claim 15 (depends on 14)

A computer-implemented manufacturing system capable of providing an authenticated semiconductor device, said computer-implemented manufacturing system configured to perform the computer-implemented manufacturing method of claim 14.

### Claim 16 (depends on 1)

A semiconductor device designed by performing the computer-implemented detecting method of claim 1.

### Claim 17 (depends on 1)

A test platform, comprising:
a hardware implementation, executing autonomously without a processor, the detecting method of claim 1.

### Claim 18 (depends on 1)

An electronics automated design application executable by a processor, said automated design application configured to generate a hardware design to perform the detecting method of claim 1.

### Claim 19 (depends on 1)

A non-transitory computer-accessible medium having stored thereon computer-executable instructions for designing a hardware design, wherein, when a hardware implementation of said design arrangement executes autonomously, to perform procedures comprising the detecting method of claim 1.