# US 12,001,385 B2 · Apparatuses, methods, and systems for instructions for loading a tile of a matrix operations accelerator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,001,385 B2 - Document ID: US12001385B2 - Status: Granted - Kind: B2 - Application number: 17/134,129 - Filed: 2020-12-24 - Published: 2022-06-30 - Granted: 2024-06-04 - Earliest claimed: 2020-12-24 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Elmoustapha Ould-Ahmed-Vall - Web page: https://patentgrep.com/patent/US12001385B2 ## CPC - G06F 15/8053: {Vector processors} - G06F 9/30032: {Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30038: {using a mask} - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/30105: {Register structure} - G06F 9/3818: {Decoding for concurrent execution} - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Systems, methods, and apparatuses relating to one or more instructions for loading a tile of a matrix operations accelerator are described. In one embodiment, a system includes a matrix operations accelerator circuit comprising a two-dimensional grid of processing elements, a plurality of registers that represents a two-dimensional matrix coupled to the two-dimensional grid of processing elements, and a coupling to a cache; and a hardware processor core coupled to the matrix operations accelerator circuit and comprising a vector register, a decoder circuit to decode a single instruction into a decoded instruction, the single instruction including a first field that identifies the two-dimensional matrix, a second field that identifies a location in the cache, and a third field that identifies the vector register, and an opcode that indicates an execution circuit of the hardware processor core is to load elements into the plurality of registers that represents the two-dimensional matrix from the location in the cache by the coupling to the cache, and load one or more elements from the vector register into the plurality of registers that represents the two-dimensional matrix by a coupling of the hardware processor core to the matrix operations accelerator circuit that is separate from the coupling to the cache, and the execution circuit of the hardware processor core to execute the decoded instruction according to the opcode. ## Claims ### Claim 1 An apparatus comprising: a matrix operations accelerator circuit comprising: a two-dimensional grid of processing elements, a plurality of registers that represents a two-dimensional matrix coupled to the two-dimensional grid of processing elements, and a coupling to a cache; and a hardware processor core coupled to the matrix operations accelerator circuit and comprising: a vector register, a decoder circuit to decode a single instruction into a decoded instruction, the single instruction including a first field that identifies the two-dimensional matrix, a second field that identifies a location in the cache, and a third field that identifies the vector register, and an opcode that indicates an execution circuit of the hardware processor core is to load elements into the plurality of registers that represents the two-dimensional matrix from the location in the cache by the coupling to the cache, and load one or more elements from the vector register into the plurality of registers that represents the two-dimensional matrix by a coupling of the hardware processor core to the matrix operations accelerator circuit that is separate from the coupling to the cache, and the execution circuit of the hardware processor core to execute the decoded instruction according to the opcode. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the one or more elements from the vector register replace one or more complete rows of the two-dimensional matrix from the location in the cache within the plurality of registers that represents the two-dimensional matrix. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the single instruction comprises a field that identifies the one or more complete rows of the two-dimensional matrix from the location in the cache to be replaced within the plurality of registers that represents the two-dimensional matrix. ### Claim 4 (depends on 2) The apparatus of claim 2, wherein the single instruction comprises a field that identifies a number of rows of the two-dimensional matrix from the location in the cache to be replaced within the plurality of registers that represents the two-dimensional matrix. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the one or more elements from the vector register replace one or more complete columns of the two-dimensional matrix from the location in the cache within the plurality of registers that represents the two-dimensional matrix. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the single instruction comprises a field that identifies the one or more complete columns of the two-dimensional matrix from the location in the cache to be replaced within the plurality of registers that represents the two-dimensional matrix. ### Claim 7 (depends on 5) The apparatus of claim 5, wherein the single instruction comprises a field that identifies a number of columns of the two-dimensional matrix from the location in the cache to be replaced within the plurality of registers that represents the two-dimensional matrix. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the execution circuit of the hardware processor core is to execute the decoded instruction according to the opcode to remove a first row or column of the two-dimensional matrix from the location in the cache within the plurality of registers that represents the two-dimensional matrix, and load the one or more elements from the vector register after a last row or last column of the two-dimensional matrix from the location in the cache within the plurality of registers that represents the two-dimensional matrix. ### Claim 9 A method comprising: decoding, by a decoder circuit of a hardware processor core coupled to a matrix operations accelerator circuit comprising a two-dimensional grid of processing elements, a plurality of registers that represents a two-dimensional matrix coupled to the two-dimensional grid of processing elements, and a coupling to a cache, a single instruction into a decoded instruction, the single instruction including a first field that identifies the two-dimensional matrix, a second field that identifies a location in the cache, and a third field that identifies a vector register of the hardware processor core, and an opcode that indicates an execution circuit of the hardware processor core is to load elements into the plurality of registers that represents the two-dimensional matrix from the location in the cache by the coupling to the cache, and load one or more elements from the vector register into the plurality of registers that represents the two-dimensional matrix by a coupling of the hardware processor core to the matrix operations accelerator circuit that is separate from the coupling to the cache; and executing the decoded instruction by the execution circuit of the hardware processor core according to the opcode. ### Claim 10 (depends on 9) The method of claim 9, wherein the one or more elements from the vector register replace one or more complete rows of the two-dimensional matrix from the location in the cache within the plurality of registers that represents the two-dimensional matrix. ### Claim 11 (depends on 10) The method of claim 10, wherein the single instruction comprises a field that identifies the one or more complete rows of the two-dimensional matrix from the location in the cache to be replaced within the plurality of registers that represents the two-dimensional matrix. ### Claim 12 (depends on 10) The method of claim 10, wherein the single instruction comprises a field that identifies a number of rows of the two-dimensional matrix from the location in the cache to be replaced within the plurality of registers that represents the two-dimensional matrix. ### Claim 13 (depends on 9) The method of claim 9, wherein the one or more elements from the vector register replace one or more complete columns of the two-dimensional matrix from the location in the cache within the plurality of registers that represents the two-dimensional matrix. ### Claim 14 (depends on 13) The method of claim 13, wherein the single instruction comprises a field that identifies the one or more complete columns of the two-dimensional matrix from the location in the cache to be replaced within the plurality of registers that represents the two-dimensional matrix. ### Claim 15 (depends on 13) The method of claim 13, wherein the single instruction comprises a field that identifies a number of columns of the two-dimensional matrix from the location in the cache to be replaced within the plurality of registers that represents the two-dimensional matrix. ### Claim 16 (depends on 9) The method of claim 9, wherein executing the decoded instruction according to the opcode removes a first row or column of the two-dimensional matrix from the location in the cache within the plurality of registers that represents the two-dimensional matrix, and loads the one or more elements from the vector register after a last row or last column of the two-dimensional matrix from the location in the cache within the plurality of registers that represents the two-dimensional matrix. ### Claim 17 A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising: decoding, by a decoder circuit of a hardware processor core coupled to a matrix operations accelerator circuit comprising a two-dimensional grid of processing elements, a plurality of registers that represents a two-dimensional matrix coupled to the two-dimensional grid of processing elements, and a coupling to a cache, a single instruction into a decoded instruction, the single instruction including a first field that identifies the two-dimensional matrix, a second field that identifies a location in the cache, and a third field that identifies a vector register of the hardware processor core, and an opcode that indicates an execution circuit of the hardware processor core is to load elements into the plurality of registers that represents the two-dimensional matrix from the location in the cache by the coupling to the cache, and load one or more elements from the vector register into the plurality of registers that represents the two-dimensional matrix by a coupling of the hardware processor core to the matrix operations accelerator circuit that is separate from the coupling to the cache; and executing the decoded instruction by the execution circuit of the hardware processor core according to the opcode. ### Claim 18 (depends on 17) The non-transitory machine readable medium of claim 17, wherein the one or more elements from the vector register replace one or more complete rows of the two-dimensional matrix from the location in the cache within the plurality of registers that represents the two-dimensional matrix. ### Claim 19 (depends on 18) The non-transitory machine readable medium of claim 18, wherein the single instruction comprises a field that identifies the one or more complete rows of the two-dimensional matrix from the location in the cache to be replaced within the plurality of registers that represents the two-dimensional matrix. ### Claim 20 (depends on 18) The non-transitory machine readable medium of claim 18, wherein the single instruction comprises a field that identifies a number of rows of the two-dimensional matrix from the location in the cache to be replaced within the plurality of registers that represents the two-dimensional matrix. ### Claim 21 (depends on 17) The non-transitory machine readable medium of claim 17, wherein the one or more elements from the vector register replace one or more complete columns of the two-dimensional matrix from the location in the cache within the plurality of registers that represents the two-dimensional matrix. ### Claim 22 (depends on 21) The non-transitory machine readable medium of claim 21, wherein the single instruction comprises a field that identifies the one or more complete columns of the two-dimensional matrix from the location in the cache to be replaced within the plurality of registers that represents the two-dimensional matrix. ### Claim 23 (depends on 21) The non-transitory machine readable medium of claim 21, wherein the single instruction comprises a field that identifies a number of columns of the two-dimensional matrix from the location in the cache to be replaced within the plurality of registers that represents the two-dimensional matrix. ### Claim 24 (depends on 17) The non-transitory machine readable medium of claim 17, wherein executing the decoded instruction according to the opcode removes a first row or column of the two-dimensional matrix from the location in the cache within the plurality of registers that represents the two-dimensional matrix, and loads the one or more elements from the vector register after a last row or last column of the two-dimensional matrix from the location in the cache within the plurality of registers that represents the two-dimensional matrix. ### Claim 25 (depends on 17) The non-transitory machine readable medium of claim 17, the method further comprising translating the single instruction into one or more instructions of a different instruction set architecture prior to the decoding, wherein executing of the one or more instructions of the different instruction set architecture is to be functionally equivalent as the executing of the decoded instruction according to the opcode.