# US 12,001,384 B2 · Processing element array and operating method thereof

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- Number: US 12,001,384 B2
- Document ID: US12001384B2
- Status: Granted
- Kind: B2
- Application number: 17/988,833
- Filed: 2022-11-17
- Published: 2024-03-14
- Granted: 2024-06-04
- Earliest claimed: 2022-09-13
- Assignees: Inventec (Pudong) Technology Corporation; Inventec Corporation
- Applicants: Inventec (Pudong) Technology Corporation; Inventec Corporation
- Inventors: Yu-Sheng Lin; Trista Pei-Chun Chen; Wei-Chao Chen
- Web page: https://patentgrep.com/patent/US12001384B2

## CPC

- G06F 15/17318: {Parallel communications techniques, e.g. gather, scatter, reduce, roadcast, multicast, all to all}
- G06F 15/80: comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15})
- G06F 9/54: Interprogram communication
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A processing element array includes N processing elements (PE) arranged linearly, N≥2, and an operating method of the PE array includes: performing a first data transmission procedure, where an initial value of I is 1 and the first data transmission procedure includes: operating, by an ith PE, according to a first datum stored in itself, and sending the first datum to other PEs for their operations, adding 1 to I when I<N, and performing the first data transmission procedure again, performing a second data transmission procedure when I is equal to N, which includes: operating, by the Jth PE, according to a second datum stored in itself, and sending the second datum to other PEs for their operations, reducing J by 1 when J>1 and the (J−1)th PE has the second datum, and performing the second data transmission procedure again.

## Claims

### Claim 1

An operation method of a processing element (PE) array, wherein the PE array comprises a plurality of PEs arranged linearly, a number of the plurality of PEs is N, Nis greater than or equal to 3, and the operation method of the PE array comprises:
performing, by the plurality of PEs, a first data transmission procedure, wherein an initial value of I is one, and the first data transmission procedure comprises:
performing, by an Ith PE of the plurality of PEs, a calculation according to a first datum stored in itself;
sending, by the Ith PE, the first datum to the plurality of PEs except the Ith PE;
performing, by the plurality of PEs except the Ith PE, the calculation according to the first datum;
when I is less than N, a value of I is changed to previous I incremented by one and performing the first data transmission procedure again by the plurality of PEs;
when I is equal to N, performing a second data transmission procedure by the plurality of PEs, wherein an initial value of J is N, and the second data transmission procedure comprises:
performing, by a Jth PE of the plurality of PEs, the calculation according to a second datum stored in itself;
sending, by the Jth PE, the second datum to the plurality of PEs except the Jth PE;
calculating, by the plurality of PEs except the Jth PE, according to the second datum; and
when J is greater than one and a (J-1)th PE stores the second datum, a value of J is changed to previous J decremented by one and performing the second data transmission procedure again by the plurality of PEs,
before performing the first data transmission procedure, further comprising:
storing a first portion of a set of data in a first order by the plurality of PEs; and
storing a second portion of the set of data in a second order by one or more of the plurality of PEs; wherein
the first order is incremented from 1 to N, the second order is opposite to the first order, the first portion includes the first datum of each of the plurality of PEs, and the second portion includes the second datum of each of the one or more of the plurality of PEs.

### Claim 2 (depends on 1)

The operation method of the PE array of claim 1, wherein the plurality of PEs stores a first portion of a set of data in a first order, one or more of the plurality of PEs stores a second portion of the set of data in a second order, the first order is incremented from one to N, the second order is opposite to the first order, the first portion includes the first datum of each of the plurality of PEs, and the second portion includes the second datum of each of the one or more of the plurality of PEs.

### Claim 3 (depends on 1)

The operation method of the PE array of claim 1 further comprising:
when J is equal to one and the Jth PE stores the first datum which is unused, performing the first data transmission procedure again by the plurality of PEs.

### Claim 4 (depends on 1)

The operation method of the PE array of claim 1, wherein sending, by the Ith PE, the first datum to the plurality of PEs except the Ith PE comprises:
performing a broadcast procedure, wherein initial values of E and F are O and the broadcast procedure comprises:
sending, by an (I+E)th PE of the plurality of PEs, the first datum to an (I+E+1)th PE of the plurality of PEs;
sending, by an (I-F))th PE of the plurality of PEs, the first datum to an (I-F-1))th PE of the plurality of PEs; and
a value of E is changed to previous E incremented by one when (I+E) is less than N, a value of F is changed to previous F decremented by one when (I-F) is greater than one, and performing the broadcast procedure again by the plurality of PEs.

### Claim 5

A processing element (PE) array comprising:
a plurality of PEs arranged linearly, wherein a number of the plurality of PEs is N and N is greater than or equal to 3, each of the plurality of PEs comprises a processor and a memory such that the plurality of PEs comprises N processors and N memories, wherein:
the N memories are configured to store P data, and P is greater than N;
a first memory to a Nth memory of the N memories are respectively configured to store a first datum to a Nth datum of the P data;
the Nth memory of the N memories is further configured to store a (N+1)th datum of the P data;
each of the N processors calculates according to one of the P data stored in one of the N memories corresponding to itself, or calculates according to another one of the P data received from other PE; and
(N+1) transmission circuits, wherein each of the (N+1) transmission circuits is electrically connected to a left PE and a right PE adjacent to each other in the N PEs, each of the (N+1) transmission circuits is configured to receive information from the left PE and sends the information to the right PE, or receive another information from the right PE and sends said another information to the left PE.

### Claim 6 (depends on 5)

The PE array of claim 5, wherein the left PE comprises a left input line and a left output line, the right PE comprises a right input line and a right output line, and each of the transmission circuits comprises:
a collector electrically connected to the left input line and the right input line and configured to collect a datum of one of the left input line and the right input line;
a detector electrically connected to the left input line and the right input line and configured to generate a left label when the left input line has the datum and generate a right label when the right input line has the datum;
a queue electrically connected to the collector and the detector, wherein the queue comprises a plurality of data rows, each of the plurality of data rows comprises a data field and a source label field, the data field is configured to store the datum of one of the left input line and the right input line, and the source label field is configured to store one of the left label and the right label; and
an output selector electrically connected to the left output line, the right output line and the queue, wherein the output selector is configured to read one of the plurality of data rows to output the datum; the output selector outputs the datum through the left output line when the source label field stores the left label, and the output selector outputs the datum through the right output line when the source label field stores the right label.

### Claim 7

A processing element (PE) array comprising:
M×N PEs arranged in M rows and N columns, wherein both M and N are greater than or equal to 2, each of the M×N PEs comprises a processor, a row memory, and a column memory such that the M×N PEs comprise M×N processors, each of the M rows has N row memories, and each of the N columns has M column memories, wherein:
the N row memories located in the same row are configured to store P data and P is greater than N;
a first row memory to a Nth row memory in the N row memories located in the same row are respectively configured to store a first datum to a Nth datum in the P data;
the Nth row memory in the N row memories located in the same row is configured to store a (N+1)th datum in the P data;
each of N processors in the same row calculates according to a datum stored in the row memory corresponding to itself, or calculates according to another datum received from other PEs;
the M column memories located in the same column are configured to store Q data and Q is greater than M;
a first column memory to a Mth column memory in the M column memories located in the same column are respectively configured to store a first datum to a Mth datum in the Q data;
the Mth column memory in the N column memories located in the same column is configured to store a (M+1)th datum in the Q data;
each of M processors in the same column calculates according to a datum stored in the column memory corresponding to itself, or calculates according to another datum received from other PEs;
(M×N−M) row transmission circuits, wherein:
each of the (M×N−M) row transmission circuits is electrically connected to a left PE and a right PE adjacent to each other in the N PEs in each of the M rows; and
each of the (M×N−M) row transmission circuits is configured to receive a row data from the left PE and send the row data to the right PE, or receive another row data from the right PE and send said another row data to the left PE; and (M×N−N) column transmission circuits, wherein:
each of the (M×N−N) column transmission circuits is electrically connected to an upper PE and a lower PE adjacent to each other in the M PEs in each of the N columns; and
each of the (M×N−N) column transmission circuits is configured to receive a column data from the upper PE and send the column data to the lower PE, or receive another column data from the lower PE and send said another column data to the upper PE.

### Claim 8 (depends on 7)

The PE array of claim 7, wherein the left PE comprises a left input line and a left output line, the right PE comprises a right input line and a right output line, and each of the row transmission circuit comprises:
a collector electrically connected to the left input line and the right input line and configured to collect a datum of one of the left input line and the right input line;
a detector electrically connected to the left input line and the right input line and configured to generate a left label when the left input line has the datum and generate a right label when the right input line has the datum;
a queue electrically connected to the collector and the detector, wherein the queue comprises a plurality of data rows, each of the plurality of data rows comprises a data field and a source label field, the data field is configured to store the datum of one of the left input line and the right input line, and the source label field is configured to store one of the left label and the right label; and
an output selector electrically connected to the left output line, the right output line and the queue, wherein the output selector is configured to read one of the plurality of data rows to output the datum; the output selector outputs the datum through the left output line when the source label field stores the left label, and the output selector outputs the datum through the right output line when the source label field stores the right label.

### Claim 9 (depends on 7)

The PE array of claim 7, wherein the upper PE comprises an upper input line and an upper output line, the lower PE comprises a lower input line and a lower output line, and each of the row transmission circuit comprises:
a collector electrically connected to the upper input line and the lower input line and configured to collect a datum of one of the upper input line and the lower input line;
a detector electrically connected to the upper input line and the lower input line and configured to generate an upper label when the upper input line has the datum and generate a lower label when the lower input line has the datum;
a queue electrically connected to the collector and the detector, wherein the queue comprises a plurality of data rows, each of the plurality of data rows comprises a data field and a source label field, the data field is configured to store the datum of one of the upper input line and the lower input line, and the source label field is configured to store one of the upper label and the lower label; and
an output selector electrically connected to the upper output line, the lower output line and the queue, wherein the output selector is configured to read one of the plurality of data rows to output the datum; the output selector outputs the datum through the upper output line when the source label field stores the upper label, and the output selector outputs the datum through the lower output line when the source label field stores the lower label.