# US 12,001,381 B2 · Reconfigurable processor and reconfigurable processor system

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- Number: US 12,001,381 B2
- Document ID: US12001381B2
- Status: Granted
- Kind: B2
- Application number: 17/769,703
- Filed: 2020-06-17
- Published: 2022-12-08
- Granted: 2024-06-04
- Earliest claimed: 2019-10-17
- Assignees: Morningcore Technology Co., China
- Applicants: Morningcore Technology Co., China
- Inventors: Weibing Wang
- Web page: https://patentgrep.com/patent/US12001381B2

## CPC

- G06F 15/7867: {with reconfigurable architecture}
- G06F 15/163: Interprocessor communication
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Provided are a reconfigurable processor and a reconfigurable processor system, where the reconfigurable processor includes: a hardware message management module (110), a memory management system (120) and an arithmetic and logic unit (130). The memory management system (120) is connected to the hardware message management module (110) and the arithmetic and logic unit (130) respectively; the hardware message management module (110) is configured to read and parse at least one hardware message, to configure a priority of each of the at least one hardware message and store each of the at least one hardware message into a memory through the memory management system (120); and the arithmetic and logic unit (130) is configured to run the at least one hardware message according to the configured priority.

## Claims

### Claim 1

A reconfigurable processor, comprising: a hardware message management module, a memory management system and an arithmetic and logic unit, wherein the memory management system is connected to the hardware message management module and the arithmetic and logic unit respectively;
wherein the hardware message management module is configured to read and parse at least one hardware message, configure a priority for each of the at least one hardware message, and store each of the at least one hardware message in a memory through the memory management system; and
the arithmetic and logic unit is configured to run the at least one hardware message according to the configured priority.

### Claim 2 (depends on 1)

The reconfigurable processor according to claim 1, wherein the hardware message management module is configured to read the at least one hardware message through a set channel, wherein each of the at least one hardware message comprises configuration flow information and data space information.

### Claim 3 (depends on 1)

The reconfigurable processor according to claim 1, wherein the arithmetic and logic unit is configured to generate a computation mode through reconfiguration, and a number of the computation mode is at least one.

### Claim 4 (depends on 1)

The reconfigurable processor according to claim 1, wherein the arithmetic and logic unit comprises at least one basic arithmetic unit of a multiplier, an adder and a comparator.

### Claim 5 (depends on 1)

The reconfigurable processor according to claim 1, wherein the memory management system comprises a general direct memory access (GDMA) subunit, a channel arbitrator and a data flow management subunit, and the memory management system is configured to perform data transmission.

### Claim 6 (depends on 1)

The reconfigurable processor according to claim 1, further comprising a register file, wherein the register file is connected to the memory management system and the arithmetic and logic unit respectively.

### Claim 7 (depends on 6)

The reconfigurable processor according to claim 6, wherein the register file is configured to configure addresses, in a memory, of the hardware messages transmitted by the memory management system, and to provide the arithmetic and logic unit with registers required for arithmetic.

### Claim 8 (depends on 1)

The reconfigurable processor according to claim 1, further comprising a power consumption management unit, wherein the power consumption management unit is connected to the hardware message management module, the memory management system and the arithmetic and logic unit respectively and is configured to perform power consumption management.

### Claim 9 (depends on 1)

A reconfigurable processor system comprising at least two cascaded reconfigurable processors according to claim 1.

### Claim 10 (depends on 9)

The reconfigurable processor system according to claim 9, wherein the at least two reconfigurable processors are configured to perform data access through a preset read channel and a preset write channel.