# US 12,001,375 B2 · Interconnect system

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- Number: US 12,001,375 B2
- Document ID: US12001375B2
- Status: Granted
- Kind: B2
- Application number: 17/523,049
- Filed: 2021-11-10
- Published: 2023-03-30
- Granted: 2024-06-04
- Earliest claimed: 2021-09-28
- Assignees: Shanghai Zhaoxin Semiconductor Co., Ltd.
- Applicants: Shanghai Zhaoxin Semiconductor Co., Ltd.
- Inventors: Weilin Wang; Xiaoliang Kang; Xuemin Zhang; Chen Chen; Yang Shi
- Web page: https://patentgrep.com/patent/US12001375B2

## CPC

- H04L 45/745: Address table lookup; Address filtering
- G06F 1/3234: Power saving characterised by the action undertaken
- G06F 9/4418: {Suspend and resume; Hibernate and awake}
- G06F 9/4812: {by interrupt, e.g. masked}
- G06F 13/1668: {Details of memory controller}
- G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)}
- G06F 13/4068: {Electrical coupling}
- G06F 13/4265: {on a point to point bus (G06F13/4247, G06F13/4282 take precedence)}
- G06F 15/7807: {System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package}
- G06F 15/7825: {Globally asynchronous, locally synchronous, e.g. network on chip}
- H04L 1/004: {by using forward error control (H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00)}
- H04L 45/02: Topology update or discovery
- H04L 45/22: {Alternate routing}
- H04L 45/42: Centralised routing
- H04L 69/324: in the data link layer [OSI layer 2], e.g. HDLC
- G06F 13/4208: {being a system bus, e.g. VME bus, Futurebus, Multibus}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A interconnect system, including a plurality of sockets and a first interconnect interface. Any two of the sockets are accessible to each other's hardware resources by transmitting a first packet and a second packet through the first interconnect interface. The first packet includes first interconnect information, used for establishing communication between the two sockets. The second packet includes a first data payload, loaded from one of the two sockets. The sockets include a first socket and a second socket, configured to be interconnected with each other through the first interconnect interface.

## Claims

### Claim 1

A interconnect system, comprising a plurality of sockets and a first interconnect interface, wherein any two of the sockets are accessible to each other's hardware resources by transmitting a first packet and a second packet through the first interconnect interface;
wherein the first packet comprises first interconnect information, configured for establishing communication that conforms with a communication protocol of the first interconnect interface between any two of the sockets;
wherein the second packet comprises a first data payload, the first data payload is data loaded from one of the sockets and transmitted to another one;
wherein the sockets comprise a first socket and a second socket, configured to be interconnected with each other through the first interconnect interface; and
wherein the number of bits of the first data payload when the first interconnect interface is congested is bigger than the number of bits of the first data payload when the first interconnect interface is not congested.

### Claim 2 (depends on 1)

The interconnect system as claimed in claim 1, wherein the first packet further comprises:
a first header, configured for indicating attributes of the first interconnect information;
a check code, configured for checking correctness of the first interconnect information.

### Claim 3 (depends on 1)

The interconnect system as claimed in claim 1, wherein number of bits of the first interconnect information is fixed.

### Claim 4 (depends on 1)

The interconnect system as claimed in claim 1, wherein the second packet further comprises:
a second header, configured for indicating attributes of the first data payload;
a second check code, configured for checking the correctness of the first data payload.

### Claim 5 (depends on 1)

The interconnect system as claimed in claim 1, wherein each of the plurality of sockets comprises a plurality of dies and a second interconnect interface, wherein any two of the dies are accessible to each other's hardware resources by transmitting a third packet through the second interconnect interface; and
wherein the dies comprise a first die and a second die, and the first die and the second die are configured to be interconnected with each other through the second interconnect interface; and
wherein the third packet comprises:
second interconnect information, configured for establishing communication between any two of the dies; and
a second data payload, loaded from one of the dies.

### Claim 6 (depends on 5)

The interconnect system as claimed in claim 5, wherein the third packet comprises:
a third header, configured for indicating attributes of the second data payload and the second interconnect information;
a third check code, configured for checking the correctness of the second data payload and the second interconnect information.

### Claim 7 (depends on 5)

The interconnect system as claimed in claim 5, wherein the number of bits of the second data payload and number of bits of the second interconnect information are fixed.

### Claim 8 (depends on 1)

The interconnect system as claimed in claim 1, wherein the hardware resources comprise a last-level cache (LLC); and
wherein the first packet and the second packet are configured for maintaining cache coherency between the LLCs of any two sockets.

### Claim 9 (depends on 1)

The interconnect system as claimed in claim 1, wherein the plurality of sockets further comprise a third socket; and
wherein the first socket and the third socket are configured to be interconnected with each other through the first interconnect interface; and
wherein the second socket and the third socket are configured to be interconnected with each other through the first interconnect interface.

### Claim 10 (depends on 1)

The interconnect system as claimed in claim 1, wherein the sockets further comprise a third socket and a fourth socket; and
wherein the first socket and the third socket are configured to be interconnected with each other through the first interconnect interface; and
wherein the second socket and the fourth socket are configured to be interconnected with each other through the first interconnect interface;
wherein the first socket, the second socket, the third socket, and the fourth socket are all on a first plane.

### Claim 11 (depends on 10)

The interconnect system as claimed in claim 10, wherein the first socket and the fourth socket are configured to be interconnected with each other through the first interconnect interface; and
wherein the second socket and the third socket are configured to be interconnected with each other through the first interconnect interface.

### Claim 12 (depends on 10)

The interconnect system as claimed in claim 10, wherein the plurality of sockets further comprise a fifth socket and a sixth socket; and
wherein the first socket and the fifth socket are configured to be interconnected with each other through the first interconnect interface; and
wherein the fourth socket and the fifth socket are configured to be interconnected with each other through the first interconnect interface; and
wherein the fifth socket and the sixth socket are configured to be interconnected with each other through the first interconnect interface; and
wherein the second socket and the sixth socket are configured to be interconnected with each other through the first interconnect interface; and
wherein the third socket and the sixth socket are configured to be interconnected with each other through the first interconnect interface; and
wherein the fifth socket is on a second plane, and the sixth socket is on a third plane; and
wherein the first plane, the second plane, and the third plane are parallel with one another, and the first plane is between the second plane and the third plane.

### Claim 13 (depends on 10)

The interconnect system as claimed in claim 10, wherein the plurality of sockets further comprise a fifth socket, a sixth socket, a seventh socket, and an eighth socket; and
wherein the fifth socket and the sixth socket are configured to be interconnected with each other through the first interconnect interface; and
wherein the fifth socket and the seventh socket are configured to be interconnected with each other through the first interconnect interface; and
wherein the sixth socket and the eighth socket are configured to be interconnected with each other through the first interconnect interface; and
wherein the seventh socket and the eighth socket are configured to be interconnected with each other through the first interconnect interface; and
wherein the first socket and the fifth socket are configured to be interconnected with each other through the first interconnect interface; and
wherein the second socket and the sixth socket are configured to be interconnected with each other through the first interconnect interface; and
wherein the third socket and the seventh socket are configured to be interconnected with each other through the first interconnect interface; and
wherein the fourth socket and the eighth socket are configured to be interconnected with each other through the first interconnect interface; and
wherein the fifth socket, the sixth socket, the seventh socket, and the eighth socket are all on a second plane, and the second plane is parallel with the first plane.

### Claim 14

A interconnect system, comprising a plurality of modules and a first interconnect interface, wherein any two of the modules are accessible to each other's hardware resources by transmitting a first packet and a second packet through the first interconnect interface;
wherein the modules are dies or chiplets;
wherein the first packet comprises first interconnect information, configured for establishing communication that conforms with a communication protocol of the first interconnect interface between any two of the modules;
wherein the second packet comprises a first data payload, the first data payload is data loaded from one of the modules and transmitted to another one; and
wherein the modules comprise a first module and a second module, configured to be interconnected with each other through the first interconnect interface; and
wherein the number of bits of the first data payload when the first interconnect interface is congested is bigger than the number of bits of the first data payload when the first interconnect interface is not congested.

### Claim 15 (depends on 14)

The interconnect system as claimed in claim 14, wherein the first packet further comprises:
a first header, configured for indicating attributes of the first interconnect information; and
a check code, configured for checking the correctness of the first interconnect information.

### Claim 16 (depends on 14)

The interconnect system as claimed in claim 14, wherein the number of bits of the first interconnect information is fixed.

### Claim 17 (depends on 14)

The interconnect system as claimed in claim 14, wherein the second packet further comprises:
a second header, configured for indicating attributes of the first data payload; and
a second check code, configured for checking the correctness of the first data payload.

### Claim 18 (depends on 14)

The interconnect system as claimed in claim 14, wherein the hardware resources comprise a last-level cache (LLC); and
wherein the first packet and the second packet are configured for maintaining cache coherency between the LLCs of any two modules.

### Claim 19 (depends on 14)

The interconnect system as claimed in claim 14, wherein the modules further comprise a third module; and
wherein the first module and the third module are configured to be interconnected with each other through the first interconnect interface; and
wherein the second module and the third module are configured to be interconnected with each other through the first interconnect interface.

### Claim 20 (depends on 14)

The interconnect system as claimed in claim 14, wherein the modules further comprise a third module and a fourth module; and
wherein the first module and the third module are configured to be interconnected with each other through the first interconnect interface; and
wherein the second module and the fourth module are configured to be interconnected with each other through the first interconnect interface;
wherein the first module, the second module, the third module, and the fourth module are all on a first plane.

### Claim 21 (depends on 18)

The interconnect system as claimed in claim 18, wherein the first module and the fourth module are configured to be interconnected with each other through the first interconnect interface; and
wherein the second module and the third module are configured to be interconnected with each other through the first interconnect interface.

### Claim 22 (depends on 18)

The interconnect system as claimed in claim 18, wherein the modules further comprise a fifth module and a sixth module; and
wherein the first module and the fifth module are configured to be interconnected with each other through the first interconnect interface; and
wherein the fourth module and the fifth module are configured to be interconnected with each other through the first interconnect interface; and
wherein the fifth module and the sixth module are configured to be interconnected with each other through the first interconnect interface; and
wherein the second module and the sixth module are configured to be interconnected with each other through the first interconnect interface; and
wherein the third module and the sixth module are configured to be interconnected with each other through the first interconnect interface; and
wherein the fifth module is on a second plane, and the sixth module is on a third plane; and
wherein the first plane, the second plane, and the third plane are parallel with one another, and the first plane is between the second plane and the third plane.

### Claim 23 (depends on 18)

The interconnect system as claimed in claim 18, wherein the modules further comprise a fifth module, a sixth module, a seventh module, and an eighth module; and
wherein the fifth module and the sixth module are configured to be interconnected with each other through the first interconnect interface; and
wherein the fifth module and the seventh module are configured to be interconnected with each other through the first interconnect interface; and
wherein the sixth module and the eighth module are configured to be interconnected with each other through the first interconnect interface; and
wherein the seventh module and the eighth module are configured to be interconnected with each other through the first interconnect interface; and
wherein the first module and the fifth module are configured to be interconnected with each other through the first interconnect interface; and
wherein the second module and the sixth module are configured to be interconnected with each other through the first interconnect interface; and
wherein the third module and the seventh module are configured to be interconnected with each other through the first interconnect interface; and
wherein the fourth module and the eighth module are configured to be interconnected with each other through the first interconnect interface; and
wherein the fifth module, the sixth module, the seventh module, and the eighth module are all on a second plane, and the second plane is parallel with the first plane.