# US 12,001,374 B2 · System and method for providing in-storage acceleration (ISA) in data storage devices

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- Number: US 12,001,374 B2
- Document ID: US12001374B2
- Status: Granted
- Kind: B2
- Application number: 17/953,011
- Filed: 2022-09-26
- Published: 2023-01-19
- Granted: 2024-06-04
- Earliest claimed: 2017-10-11
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Ramdas Kachare; Fred Worley; Xuebin Yao
- Web page: https://patentgrep.com/patent/US12001374B2

## CPC

- G06F 13/4234: {being a memory bus}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0611: {in relation to response time}
- G06F 3/0632: {by initialisation or re-initialisation of storage systems}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0661: {Format or protocol conversion arrangements}
- G06F 3/067: {Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 9/4411: {Configuring for operating with peripheral devices; Loading of device drivers}
- G06F 13/1668: {Details of memory controller}
- G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)}
- G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus}
- G06F 13/4295: {using an embedded synchronisation}
- H04L 49/356: for storage area networks
- G06F 2213/0008: High speed serial bus, e.g. Fiber channel
- G06F 2213/0026: PCI express
- G06N 20/00: Machine learning
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A data storage device includes: a data storage medium; a processor comprising a plurality of processor cores; a plurality of application acceleration black-box (AABB) slots including reconfigurable logic blocks, interconnects, and memories; a host interface that receives a host command from a remote application running on a remote host computer, wherein the host command includes an image file including a register-transfer level (RTL) bitstream and a firmware driver; and a configuration controller that downloads the RTL bitstream to an AABB slot of the plurality of AABB slots and reconfigure the AABB slot, and load the firmware driver to a processor core of the processor. The processor core loaded with the firmware driver runs a data acceleration process of the remote application to access and process data stored in the data storage medium using the RTL bitstream downloaded in the AABB slot.

## Claims

### Claim 1

A bridge device comprising:
a first interface for accessing data stored in a non-transitory data storage medium of a data storage device;
a processor;
a processing circuit;
an interconnect;
a second interface for receiving a command from a computing device for configuring the data storage device to run a first process in the bridge device, wherein the command includes first configuration data, first instructions and a first identifier; and
a controller for reconfiguring at least one of a first portion of the processing circuit associated with the first identifier or the interconnect by loading first configuration data into the processing circuit and interconnecting the processing circuit via the interconnect,
wherein the controller is configured to receive the command via the second interface and load the processor with the first instructions,
wherein the processor is configured to run the first process by accessing the data stored in the non-transitory data storage medium of the data storage device via the first interface and process the data using the first portion of the processing circuit and the interconnect that are reconfigured by the controller according to the command,
wherein the controller is configured to receive second configuration data, second instructions, and a second identifier, and configure a second portion of the processing circuit associated with the second identifier based on the second configuration data, and load the second instructions to the processor for running a second process based on the second configuration data and the second instructions.

### Claim 2 (depends on 1)

The bridge device of claim 1, wherein the first configuration data includes a first register transfer level (RTL) bitstream.

### Claim 3 (depends on 1)

The bridge device of claim 1, wherein the first instructions include first driver instructions.

### Claim 4 (depends on 1)

The bridge device of claim 1, wherein the controller is configured to receive third configuration data and third instructions, and replace the first configuration data with the third configuration data and load the third instructions to the processor for running a third process based on the third configuration data and the third instructions.

### Claim 5 (depends on 1)

The bridge device of claim 1, wherein the processing circuit includes an embedded processor.

### Claim 6 (depends on 1)

The bridge device of claim 1, wherein the command includes a management command for enabling, disabling, or discarding the first configuration data or the first instructions.

### Claim 7 (depends on 1)

The bridge device of claim 1, wherein the command includes a communication command to communicate with a slot including the processing circuit and the interconnect, wherein the slot is associated with the first identifier, wherein the communication command includes the first identifier associated with the slot.

### Claim 8 (depends on 1)

The bridge device of claim 1, wherein the processor loaded with the first instructions is configured to access the data stored in the non-transitory data storage medium via the first interface and run the first process using an application program interface (API) call that is agnostic to an application associated with the first process.

### Claim 9 (depends on 1)

The bridge device of claim 1, wherein the processing circuit and the interconnect are included in a slot that includes at least one of a logic area, a look-up table (LUT), a random-access memory (RAM) block, a hard macro, a clock signal, or a reset signal.

### Claim 10 (depends on 1)

The bridge device of claim 1, wherein the processing circuit and the interconnect are included in a slot that includes at least one of a programmable clock/reset, an advanced extensible interface (AXI) to the processor, a double data rate (DDR) memory interface, a peripheral component interconnect express (PCIe) interface, or an Ethernet interface.

### Claim 11

A data storage device comprising:
a non-transitory data storage medium;
a processing circuit; and
a controller including a processor,
wherein the controller is configured to receive a command from a computing device, the command including first configuration data, first instructions, and a first identifier,
wherein the controller is configured to configure a first portion of the processing circuit associated with the first identifier based on the first configuration data, and load the first instructions to the processor for running a first process by accessing and processing local data stored in the non-transitory data storage medium using the first portion of the processing circuit,
wherein the controller is configured to receive second configuration data, second instructions, and a second identifier, and
wherein the controller is configured to configure a second portion of the processing circuit associated with the second identifier based on the second configuration data, and load the second instructions to the processor for running a second process based on the second configuration data and the second instructions.

### Claim 12 (depends on 11)

The data storage device of claim 11, wherein the data storage device includes a solid-state drive (SSD).

### Claim 13 (depends on 11)

The data storage device of claim 11, wherein the processing circuit includes an embedded processor.

### Claim 14 (depends on 11)

The data storage device of claim 11, wherein the first configuration data includes a first register transfer level (RTL) bitstream, and the second configuration data includes a second RTL bitstream.

### Claim 15 (depends on 11)

The data storage device of claim 11, wherein the first instructions include first driver instructions and the second instructions include second driver instructions.

### Claim 16 (depends on 11)

The data storage device of claim 11, wherein the command includes a management command for enabling, disabling, or discarding the first configuration data or the first instructions.

### Claim 17 (depends on 11)

The data storage device of claim 11, wherein the command includes a communication command to communicate with a slot including the processing circuit, wherein the slot is associated with the first identifier.

### Claim 18 (depends on 11)

The data storage device of claim 11, wherein the processor loaded with the first instructions is configured to access data stored in the non-transitory data storage medium and run the first process using an application program interface (API) call that is agnostic to an application associated with the first process.

### Claim 19 (depends on 11)

The data storage device of claim 11, wherein the processing circuit is included in a slot that includes at least one of a logic area, a look-up table (LUT), a random-access memory (RAM) block, a hard macro, a clock signal, or a reset signal.

### Claim 20 (depends on 11)

The data storage device of claim 11, wherein the processing circuit is included in a slot that includes tat least one of a programmable clock/reset, an advanced extensible interface (AXI) to the processor, a double data rate (DDR) memory interface, a peripheral component interconnect express (PCIe) interface, or an Ethernet interface.