# US 12,001,373 B2 · Dynamic allocation of peripheral component interconnect express bus numbers

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- Number: US 12,001,373 B2
- Document ID: US12001373B2
- Status: Granted
- Kind: B2
- Application number: 17/842,384
- Filed: 2022-06-16
- Published: 2023-12-21
- Granted: 2024-06-04
- Earliest claimed: 2022-06-16
- Assignees: Dell Products L.P.
- Applicants: Dell Products L.P.
- Inventors: Wei G. Liu; Alberto D. Perez Guevara; Sanjeev Singh
- Web page: https://patentgrep.com/patent/US12001373B2

## CPC

- G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus}
- G06F 9/5044: {considering hardware capabilities}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G06F 2213/0026: PCI express
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An information handling system may detect whether each one of a plurality of peripheral component interconnect express (PCIe) slots is populated or unpopulated, and update a PCIe bus configuration map to indicate whether each of the PCIe slots is populated. The system may also allocate PCIe bus resources to each of the PCIe slots based on the PCIe bus configuration map, wherein the allocating of the PCIe bus resources includes prioritizing populated PCIe slots over unpopulated PCIe slots.

## Claims

### Claim 1

A method performed at power-on self-test, the method comprising:
detecting, by a processor, whether each one of a plurality of peripheral component interconnect express (PCIe) slots is populated or unpopulated;
updating a PCIe bus configuration map to indicate whether each one of the PCIe slots is populated or unpopulated;
allocating PCIe bus resources to each one of the PCIe slots based on the PCIe bus configuration map, wherein the allocating of the PCIe bus resources includes prioritizing populated PCIe slots over unpopulated PCIe slots; and
disabling a root port associated with an unpopulated PCIe slot.

### Claim 2 (depends on 1)

The method of claim 1, wherein the detecting whether each one of the PCIe slots is populated or unpopulated is based on a value of presence detect state bit associated with each of the PCIe slots.

### Claim 3 (depends on 1)

The method of claim 1, further comprising disabling a clock associated with an unpopulated PCIe slot.

### Claim 4 (depends on 1)

The method of claim 1, wherein the allocating of the PCIe bus resources includes generating a resource balancing table.

### Claim 5 (depends on 4)

The method of claim 4, further comprising transmitting the resource balancing table to a reference code of a basic input/output system.

### Claim 6 (depends on 1)

The method of claim 1, further comprising determining how many PCIe slots are included in an information handling system.

### Claim 7 (depends on 1)

The method of claim 1, wherein the allocating of the PCIe bus resources includes allocating a minimum number of the PCIe bus resources to unpopulated PCIe slots.

### Claim 8

An information handling system, comprising:
a processor; and
a memory device storing code that when executed causes the processor to perform operations, the operations including:
detecting whether each one of a plurality of peripheral component interconnect express (PCIe) slots is populated or unpopulated;
updating a PCIe bus configuration map to indicate whether each of the PCIe slots is populated or unpopulated;
allocating PCIe bus resources to each of the PCIe slots based on the PCIe bus configuration map, wherein the allocating of the PCIe bus resources includes prioritizing populated PCIe slots over unpopulated PCIe slots: and
disabling a clock associated with an unpopulated PCIe slot.

### Claim 9 (depends on 8)

The information handling system of claim 8, wherein the detecting whether each of the PCIe slots is populated or unpopulated is based on a value of presence detect state bit associated with each of the PCIe slots.

### Claim 10 (depends on 8)

The information handling system of claim 8, further comprising disabling a root port associated with an unpopulated PCIe slot.

### Claim 11 (depends on 8)

The information handling system of claim 8, wherein the allocating of the PCIe bus resources includes generating a resource balancing table.

### Claim 12 (depends on 11)

The information handling system of claim 11, further comprising transmitting the resource balancing table to a reference code of a basic input/output system.

### Claim 13 (depends on 8)

The information handling system of claim 8, further comprising determining how many PCIe slots are included in the information handling system.

### Claim 14 (depends on 8)

The information handling system of claim 8, wherein the allocating of the PCIe bus resources includes allocating a minimum number of the PCIe bus resources to unpopulated PCIe slots.

### Claim 15

A non-transitory computer-readable media to store instructions that are executable to perform operations comprising:
detecting whether each of a plurality of peripheral component interconnect express (PCIe) slots is populated;
updating a PCIe bus configuration map to indicate whether each slot is populated;
allocating PCIe bus resources to each slot based on the PCIe bus configuration map, wherein the allocating of the PCIe bus resources includes prioritizing populated PCIe slots over unpopulated PCIe slots, wherein the allocating of the PCIe bus resources includes generating a resource balancing table; and
transmitting the resource balancing table to a reference code of a basic input/output system.

### Claim 16 (depends on 15)

The non-transitory computer-readable media of claim 15, wherein the detecting whether each of the PCIe slots is populated or unpopulated is based on a value of presence detect state bit associated with each of the PCIe slots.

### Claim 17 (depends on 15)

The non-transitory computer-readable media of claim 15, the operations further comprising disabling a root port associated with an unpopulated PCIe slot.

### Claim 18 (depends on 15)

The non-transitory computer-readable media of claim 15, the operations further comprising disabing a dock associated with an unpopulated PCIe slot.

### Claim 19 (depends on 15)

The non-transitory computer-readable media of claim 15, wherein the operations further comprising mapping each PCIe slot to a corresponding PCIe stack.

### Claim 20 (depends on 15)

The non-transitory computer-readable media of claim 15, the operations further comprising determining how many PCIe slots are included in an information handling system.