# US 12,001,372 B2 · Autonomous entry and exit of low latency datapath in PCIe applications

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- Number: US 12,001,372 B2
- Document ID: US12001372B2
- Status: Granted
- Kind: B2
- Application number: 17/694,106
- Filed: 2022-03-14
- Published: 2023-09-14
- Granted: 2024-06-04
- Earliest claimed: 2022-03-14
- Assignees: Avago Technologies International Sales Pte. Limited
- Applicants: Avago Technologies International Sales Pte. Limited
- Inventors: Jeffrey Ronald Dorst
- Web page: https://patentgrep.com/patent/US12001372B2

## CPC

- G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus}
- G06F 13/4295: {using an embedded synchronisation}
- G06F 9/30123: {according to context, e.g. thread buffers}
- G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A PCIe retimer includes read-only vendor registers with low latency mode entry and exit values. In-band low latency switching logic monitors the output of an elastic buffer for read commands of the vendor registers and, when such read commands are received, reads the corresponding address and switches a multiplexer between a link training data path and a low latency data path based on the return value of the read operation. Read commands, and therefore control of data path switching, is handled entirely in-band. Return values of the read operations indicate success or failure of mode switching to the root complex.

## Claims

### Claim 1

A PCIe retimer comprising:
an elastic buffer;
a link training and status state machine;
a multiplexer; and
switching logic in data communication with the elastic buffer and the multiplexer, the switching logic comprising:
a first register configured with a first bit value;
a second register configured with a second bit value; and
processing logic configured to:
identify a read signal from the elastic buffer, the read signal configured to instruct the switching logic to read one of the first register or the second register;
read the register indicated by the read signal; and
apply a signal to the multiplexer corresponding to the first bit value or the second bit value depending on which of the first register or second register was read,
wherein:
the first bit value puts the multiplexer in a configuration to utilize the link training and status state machine; and
the second bit value puts the multiplexer in a configuration to bypass the link training and status state machine;
wherein the PCIe retimer is configured to receive a first signal and boost the first signal by regenerating the first signal as a second signal.

### Claim 2 (depends on 1)

The PCIe retimer of claim 1, wherein the switching logic further comprises:
a first overload register having a register address corresponding to the first register; and
a second overload register having a register address corresponding to the second register.

### Claim 3 (depends on 1)

The PCIe retimer of claim 1, wherein the processing logic is further configured to:
receive a signal from an upstream component instructing the PCIe retimer to enter a low latency mode; and
populate the elastic buffer with the received signal to instruct the switching logic to put the multiplexer in the configuration to bypass the link training and status state machine.

### Claim 4 (depends on 3)

The PCIe retimer of claim 3, wherein the received signal comprises a Lane Margin read command.

### Claim 5 (depends on 1)

The PCIe retimer of claim 1, wherein the processing logic is further configured to return a return code to a root complex based on a success or failure to apply the signal to the multiplexer.

### Claim 6 (depends on 1)

The PCIe retimer of claim 1, wherein the processing logic is further configured to:
continuously monitor the elastic buffer for a read signal while the multiplexer is in a low latency mode;
identify a read signal configured to instruct the switching logic to read the first register; and
apply a signal to the multiplexer corresponding to the first bit value, wherein the read signal is delivered entirely in-band.

### Claim 7 (depends on 1)

The PCIe retimer of claim 1, wherein the signal to the multiplexer comprises a read value returned when reading the vendor address corresponding to the vendor address signal.

### Claim 8

A PCIe device comprising a retimer configured to receive a first signal and boost the first signal by regenerating the first signal as a second signal, the retimer comprising:
a receiver;
a transmitter; and
a PCIe retimer comprising:
an elastic buffer;
a link training and status state machine;
a multiplexer; and
switching logic in data communication with the elastic buffer and the multiplexer, the switching logic comprising:
a first register configured with a first bit value;
a second register configured with a second bit value; and
processing logic configured to:
receive a low latency mode entry/exit signal via the receiver;
populate the elastic buffer with the low latency mode entry/exit signal;
identify a low latency mode entry/exit signal from the elastic buffer, the low latency mode entry/exit signal configured to instruct the switching logic to read one of the first register or the second register;
read register indicated by the low latency mode entry/exit signal;
apply a signal to the multiplexer corresponding to the first bit value or the second bit value based on the low latency mode entry/exit,
wherein:
the first bit value puts the multiplexer in a configuration to utilize the link training and status state machine; and
the second bit value puts the multiplexer in a configuration to utilize a low latency data path directly linking the receiver to the transmitter.

### Claim 9 (depends on 8)

The PCIe device of claim 8, wherein the switching logic further comprises:
a first overload register having a register address corresponding to the first register; and
a second overload register having a register address corresponding to the second register.

### Claim 10 (depends on 8)

The PCIe device of claim 8, wherein the low latency mode entry/exit signal comprises a Lane Margin read command.

### Claim 11 (depends on 8)

The PCIe device of claim 8, wherein the processing logic is further configured to return a return code to a root complex based on a success or failure to apply the signal to the multiplexer.

### Claim 12 (depends on 8)

The PCIe device of claim 8, wherein the processing logic is further configured to:
continuously monitor the elastic buffer for a low latency mode entry/exit signal while the multiplexer is in a low latency mode;
identify a low latency mode entry/exit signal corresponding to the first register; and
apply a signal to the multiplexer corresponding to the first bit value,
wherein the low latency mode entry/exit signal is delivered entirely in-band.

### Claim 13 (depends on 8)

The PCIe device of claim 8, wherein the signal to the multiplexer comprises a read value returned when reading the vendor address corresponding to the vendor address signal.

### Claim 14

A system comprising:
a first device including a PCIe interface;
a second device including a PCIe interface; and
a PCIe retimer electronically interposed between the first device and the second device, the PCIe retimer being configured to receive a first signal from the first device and boost the first signal by regenerating the first signal as a second signal, the second signal being output to the second device, the PCIe retimer comprising:
an elastic buffer;
a link training and status state machine;
a multiplexer; and
switching logic in data communication with the elastic buffer and the multiplexer, the switching logic comprising:
a first register configured with a first bit value;
a second register configured with a second bit value; and
processing logic configured to:
identify a read signal from the elastic buffer, the read signal configured to instruct the switching logic to read one of the first register or second vendor address;
read the register corresponding indicated by the read signal;
apply a signal to the multiplexer corresponding to the first bit value or the second bit value based on the read signal,
wherein:
the first bit value puts the multiplexer in a configuration to utilize the link training and status state machine; and
the second bit value puts the multiplexer in a configuration to bypass the link training and status state machine.

### Claim 15 (depends on 14)

The system of claim 14, wherein the switching logic further comprises:
a first overload register address corresponding to the first register; and
a second overload register address corresponding to the second register.

### Claim 16 (depends on 14)

The system of claim 14, wherein the processing logic is further configured to:
receive a signal from the first device instructing the PCIe retimer to enter a low latency mode; and
populate the elastic buffer with the received signal.

### Claim 17 (depends on 16)

The system of claim 16, wherein the low latency mode entry signal comprises a Lane Margin read command.

### Claim 18 (depends on 14)

The system of claim 14, wherein the processing logic is further configured to return a return code to a root complex based on a success or failure to apply the signal to the multiplexer.

### Claim 19 (depends on 14)

The system of claim 14, wherein the processing logic is further configured to:
continuously monitor the elastic buffer for a read signal while the multiplexer is in a low latency mode;
identify a read signal corresponding to the first register; and
apply a signal to the multiplexer corresponding to the first bit value,
wherein the read signal is delivered entirely in-band.

### Claim 20 (depends on 14)

The system of claim 14, wherein the signal to the multiplexer comprises a read value returned when reading the register address corresponding to the read signal.