# US 12,001,370 B2 · Multi-node memory address space for PCIe devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,001,370 B2 - Document ID: US12001370B2 - Status: Granted - Kind: B2 - Application number: 17/565,601 - Filed: 2021-12-30 - Published: 2023-07-06 - Granted: 2024-06-04 - Earliest claimed: 2021-12-30 - Assignees: Advanced Micro Devices, Inc. - Applicants: Advanced Micro Devices, Inc. - Inventors: Brock A. Taylor - Web page: https://patentgrep.com/patent/US12001370B2 ## CPC - G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus} - G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory} - G06F 12/0284: {Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163)} - G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)} - G06F 13/1668: {Details of memory controller} - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - G06F 13/404: {with address mapping} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 12/1072: Decentralised address translation, e.g. in distributed shared memory systems - G06F 12/1081: for peripheral access to main memory, e.g. direct memory access [DMA] - G06F 2212/1024: Latency reduction - G06F 2212/1028: Power efficiency - G06F 2212/657: Virtual address space management - G06F 2213/0026: PCI express - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A device in an interconnect network is provided. The device comprises an end point processor comprising end point memory and an interconnect network link in communication with an interconnect network switch. The device is configured to issue, by the end point processor, a request to send data from the end point memory to other end point memory of another end point processor of another device in the interconnect network and provide, to the interconnect network switch, the request using memory addresses from a global memory address map which comprises a first global memory address range for the end point processor and a second global memory address range for the other end point processor. ## Claims ### Claim 1 A device in an interconnected network, the device comprising: a plurality of end point processors each comprising end point memory; an interconnect network link in communication with an interconnect network switch; and a local address space comprising local addresses of the end point memory of each of the end point processors; the device configured to: issue, by an end point processor of the plurality of end point processors, a request to send data from the end point memory of the end point processor to end point memory of another end point processor of another device in the interconnect network; and provide, to the interconnect network switch, the request using memory addresses from a global memory address map which comprises information identifying the global addresses for the device and the other device and global memory address ranges for each of the plurality of end point processors of the device and each of a plurality of end point processors of the other device. ### Claim 2 (depends on 1) The device of claim 1, wherein the end point processor of the device is a first GPU and the other end point processor of the other device is a second GPU. ### Claim 3 (depends on 1) The device of claim 1 wherein the interconnect network is a peripheral component interconnect express (PCIe) network. ### Claim 4 (depends on 1) The device of claim 1, wherein the first global memory address range and the second global memory address range are non-overlapping address ranges. ### Claim 5 (depends on 1) The device of claim 1, wherein the end point processor and the other end point processor are a same processor type, and the first global memory address range and the second global memory address range are part of a continuous global address range for processors of the same processor type. ### Claim 6 (depends on 1) The device of claim 1, wherein the device is configured to map local addresses of the end point memory of the end point processor to the first global memory address range. ### Claim 7 (depends on 1) The device of claim 1, wherein the local address space comprises a device aperture and the device is further configured to map the local addresses of the end point memory of each end point processor of the device to a non-overlapping global address range using the corresponding device aperture. ### Claim 8 (depends on 1) The device of claim 1, wherein the device is configured to: skip read and write operations used for inter-device data transfers; and map local addresses of the end point memory to the first global memory address range by translating local addresses of the skipped read and write operations. ### Claim 9 A method for accessing memory in an interconnect network, the method comprising: issuing, by an end point processor of a plurality of end point processors of a first device in the interconnect network, a request to send data from end point memory of the end point processor to end point memory of another end point processor of a second device in communication with the first device via an interconnect network switch, wherein the first device comprises a local address space comprising local addresses of the end point memory of each of the plurality of end point processors; and providing, to the interconnect network switch, the request using memory addresses from a global memory address map which comprises information identifying the global addresses for the first device and the second device and global memory address ranges for each of a plurality of end point processors of the first device and each of a plurality of end point processors of the second device. ### Claim 10 (depends on 9) The method of claim 9, wherein the end point processor of the first device is a first GPU and the other end point processor of the second device is a second GPU. ### Claim 11 (depends on 9) The method of claim 9, wherein the interconnect network is a peripheral component interconnect express (PCIe) network. ### Claim 12 (depends on 9) The method of claim 9, wherein the first global memory address range and the second global memory address range are non-overlapping address ranges. ### Claim 13 (depends on 9) The method of claim 9, wherein the end point processor and the other end point processor are a same processor type, and the first global memory address range and the second global memory address range are part of a continuous global address range for processors of the same processor type. ### Claim 14 (depends on 9) The method of claim 9, further comprising mapping local addresses of the end point memory of each end point processor of the first device to the first global memory address range. ### Claim 15 (depends on 9) The method of claim 9, further comprising: skipping read and write operations used for inter-device data transfers; and mapping local addresses of the end point memory to the first global memory address range by translating the local addresses of the skipped read and write operations. ### Claim 16 An interconnect network comprising: an interconnect network switch; a first device comprising: a plurality of first end point processors each comprising first end point memory; and a first interconnect network link in communication with the interconnect network switch; and a first local address space comprising local addresses of the first end point memory of each of the plurality of first end point processors; a second device comprising: a plurality of second end point processors each comprising second end point memory; and a second interconnect link in communication with the interconnect network switch; and a second local address space comprising local addresses of the second end point memory of each of the plurality of second end point processors; the first device configured to: issue, by a first end point processor of the plurality of first end point processors, a request to send data from the first end point memory of the first end point processor to the second end point memory of a second end point processor of the plurality of second end point processors; and provide, to the interconnect network switch, the request using memory addresses from a global memory address map which comprises information identifying the global addresses for the first device and the second device and global memory address ranges for each of the plurality of end point processors of the first device and the second device. ### Claim 17 (depends on 16) The interconnect network of claim 16, wherein the first end point processor of the first device is a first GPU and the second end point processor of the second device is a second GPU. ### Claim 18 (depends on 16) The interconnect network of claim 16, wherein the interconnect network is a peripheral component interconnect express (PCIe) network. ### Claim 19 (depends on 16) The interconnect network of claim 16, wherein the first global memory address range and the second global memory address range are non-overlapping address ranges. ### Claim 20 (depends on 16) The interconnect network of claim 16, wherein the interconnect network switch is configured to route the request to the second device using a global identifier, from the global memory address map, identifying the second device.