# US 12,001,368 B2 · Memory devices and systems with parallel impedance adjustment circuitry and methods for operating the same

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- Number: US 12,001,368 B2
- Document ID: US12001368B2
- Status: Granted
- Kind: B2
- Application number: 16/752,551
- Filed: 2020-01-24
- Published: 2020-05-21
- Granted: 2024-06-04
- Earliest claimed: 2017-11-09
- Applicants: Lodestar Licensing Group LLC
- Inventors: Hyun Yoo Lee
- Web page: https://patentgrep.com/patent/US12001368B2

## CPC

- G06F 13/4086: {Bus impedance matching, e.g. termination}
- G06F 13/00: Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor G06F9/46}; multiprocessor systems G06F15/16 )
- G11C 29/022: {in I/O circuitry}
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/26: Accessing multiple arrays (G11C29/24 takes precedence)
- G11C 29/50008: {of impedance}
- H04L 25/0278: {Arrangements for impedance matching}
- H05K 1/0246: {Termination of transmission lines}
- H05K 1/025: {Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance (H05K1/024 and H05K1/0243 take precedence; for semiconductor devices H10W44/20)}
- G11C 2029/2602: {Concurrent test}
- G11C 2207/2254: Calibration
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.

## Claims

### Claim 1

A memory device, comprising:
a plurality of impedance adjustment circuitries, each impedance adjustment circuitry configured to provide a corresponding impedance to a received clock signal having a clock impedance;
wherein the corresponding impedances of the plurality of impedance adjustment circuitries provide a combined impedance based on the clock impedance during a read operation directed to memory cells corresponding to one of the plurality of impedance adjustment circuitries, and
wherein the corresponding impedance of each of the plurality of impedance adjustment circuitries is an integer multiple of the clock impedance.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the clock signal is a differential clock signal.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the clock signal comprises a data clock signal WCK.

### Claim 4 (depends on 3)

The memory device of claim 3, further comprising:
a plurality of terminals, each terminal of the plurality of terminals coupled to a corresponding one of the plurality of impedance matching circuitries and configured to receive the data clock signal WCK.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the combined impedance is equivalent to the clock impedance when the plurality of impedance adjustment circuitries are connected to the received clock signal and in parallel with each another.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein each of the plurality of impedance adjustment circuitries include impedance detection circuitry configured to detect the clock impedance.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein each of the plurality of impedance adjustment circuitries include impedance multiplier circuitry configured to generate the corresponding impedance as a multiple of the clock impedance.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein a single semiconductor die comprises the plurality of impedance adjustment circuitries.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein a first semiconductor die comprises a first one of the plurality of impedance adjustment circuitries and a second semiconductor die comprises a second one of the plurality of impedance adjustment circuitries.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein the corresponding impedances of the plurality of impedance adjustment circuitries are equal.

### Claim 11 (depends on 1)

The memory device of claim 1, wherein the corresponding impedance of a first one of the plurality of impedance adjustment circuitries differs from the corresponding impedance of a second one of the plurality of impedance adjustment circuitries.

### Claim 12 (depends on 1)

The memory device of claim 1, wherein the memory device is a dynamic random access memory (DRAM) device.

### Claim 13

A method comprising:
receiving a clock signal having a clock impedance at a first memory device;
receiving the clock signal having the clock impedance at a second memory device; and
adjusting a first impedance at the first memory device and a second impedance at the second memory device to provide a combined impedance that is based at least in part on the clock impedance during a read operation directed to memory cells corresponding to the first memory device,
wherein each of the first impedance and the second impedance is an integer multiple of the clock impedance.

### Claim 14 (depends on 13)

The method of claim 13, wherein the clock signal is a differential clock signal.

### Claim 15 (depends on 13)

The method of claim 13, wherein the clock signal comprises a data clock signal WCK.

### Claim 16 (depends on 15)

The method of claim 15, wherein:
receiving the clock signal at the first memory device comprises receiving the data clock signal WCK at a first terminal of the first memory device; and
receiving the clock signal at the second memory device comprises receiving the data clock signal WCK at a second terminal of the second memory device.

### Claim 17 (depends on 13)

The method of claim 13, further comprising:
detecting the clock impedance at the first memory device and at the second memory device.

### Claim 18 (depends on 13)

The method of claim 13, wherein the first impedance is equivalent to the second impedance.

### Claim 19 (depends on 13)

The method of claim 13, wherein the first impedance differs from the second impedance.