# US 12,001,367 B2 · Multi-die integrated circuit with data processing engine array

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,001,367 B2
- Document ID: US12001367B2
- Status: Granted
- Kind: B2
- Application number: 18/320,147
- Filed: 2023-05-18
- Published: 2023-09-14
- Granted: 2024-06-04
- Earliest claimed: 2020-09-28
- Assignees: Xilinx, Inc.
- Applicants: Xilinx, Inc.
- Inventors: Juan J. Noguera Serra; Tim Tuan; Sridhar Subramanian
- Web page: https://patentgrep.com/patent/US12001367B2

## CPC

- G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)}
- G06F 15/7807: {System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package}
- G06F 13/1668: {Details of memory controller}
- G06F 15/7825: {Globally asynchronous, locally synchronous, e.g. network on chip}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An integrated circuit includes an interposer and a die coupled to the interposer. The die includes a first data processing engine (DPE) array and a second DPE array. The first DPE array includes a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs. The second DPE array includes a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs. The integrated circuit includes one or more other dies having a first die interface coupled to, and configured to communicate with, the first DPE interface via the interposer and a second die interface coupled to, and configured to communicate with, the second DPE interface via the interposer.

## Claims

### Claim 1

A multi-die integrated circuit, comprising:
an interposer;
a die coupled to the interposer, wherein the die includes a first data processing engine (DPE) array and a second DPE array;
wherein the first DPE array includes a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs;
wherein the second DPE array includes a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs; and
one or more other dies having a first die interface coupled to, and configured to communicate with, the first DPE interface via the interposer and a second die interface coupled to, and configured to communicate with, the second DPE interface via the interposer.

### Claim 2 (depends on 1)

The multi-die integrated circuit of claim 1, wherein the first die interface and the second die interface are disposed in a same die of the one or more other dies.

### Claim 3 (depends on 1)

The multi-die integrated circuit of claim 1, wherein the first die interface and the second die interface are disposed in different dies of the one or more other dies.

### Claim 4 (depends on 1)

The multi-die integrated circuit of claim 1, wherein the first DPE interface and the second DPE interface are matched.

### Claim 5 (depends on 1)

The multi-die integrated circuit of claim 1, wherein the first DPE interface implements an interface of a first type and the second DPE interface implements an interface of a second and different type.

### Claim 6 (depends on 1)

The multi-die integrated circuit of claim 1, wherein the first DPE array and the second DPE array are isolated from one another.

### Claim 7 (depends on 6)

The multi-die integrated circuit of claim 6, wherein no DPE of the first plurality of DPEs of the first DPE array has a connection in the die to any DPE of the second plurality of DPEs of the second DPE array.

### Claim 8 (depends on 1)

The multi-die integrated circuit of claim 1, wherein one or more DPEs of the first plurality of DPEs of the first DPE array are coupled to one or more DPEs of the second plurality of DPEs of the second DPE array.

### Claim 9 (depends on 8)

The multi-die integrated circuit of claim 8, wherein the first DPE interface is isolated from the second DPE interface.

### Claim 10 (depends on 9)

The multi-die integrated circuit of claim 9, wherein the first DPE interface includes a first plurality of tiles and the second DPE interface includes a second plurality of tiles, and wherein no tile of the first plurality of tiles of the first DPE interface has a connection in the die to any tile of the second plurality of tiles of the second DPE interface.

### Claim 11

A multi-die integrated circuit, comprising:
a package substrate;
one or more interconnect bridge dies coupled to the package substrate;
a die coupled to the package substrate and the one or more interconnect bridge dies, wherein the die includes a first data processing engine (DPE) array and a second DPE array;
wherein the first DPE array includes a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs;
wherein the second DPE array includes a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs; and
one or more other dies having a first die interface coupled to, and configured to communicate with, the first DPE interface via the one or more interconnect bridge dies and a second die interface coupled to, and configured to communicate with, the second DPE interface via the one or more interconnect bridge dies.

### Claim 12 (depends on 11)

The multi-die integrated circuit of claim 11, wherein the first die interface and the second die interface are disposed in a same die of the one or more other dies.

### Claim 13 (depends on 11)

The multi-die integrated circuit of claim 11, wherein the first die interface and the second die interface are disposed in different dies of the one or more other dies.

### Claim 14 (depends on 11)

The multi-die integrated circuit of claim 11, wherein the first DPE interface and the second DPE interface are matched.

### Claim 15 (depends on 11)

The multi-die integrated circuit of claim 11, wherein the first DPE interface implements an interface of a first type and the second DPE interface implements an interface of a second and different type.

### Claim 16 (depends on 11)

The multi-die integrated circuit of claim 11, wherein the first DPE array and the second DPE array are isolated from one another.

### Claim 17 (depends on 16)

The multi-die integrated circuit of claim 16, wherein no DPE of the first plurality of DPEs of the first DPE array has a connection in the die to any DPE of the second plurality of DPEs of the second DPE array.

### Claim 18 (depends on 11)

The multi-die integrated circuit of claim 11, wherein one or more DPEs of the first plurality of DPEs of the first DPE array are coupled to one or more DPEs of the second plurality of DPEs of the second DPE array.

### Claim 19 (depends on 18)

The multi-die integrated circuit of claim 18, wherein the first DPE interface is isolated from the second DPE interface.

### Claim 20 (depends on 19)

The multi-die integrated circuit of claim 19, wherein the first DPE interface includes a first plurality of tiles and the second DPE interface includes a second plurality of tiles, and wherein no tile of the first plurality of tiles of the first DPE interface has a connection in the die to any tile of the second plurality of tiles of the second DPE interface.