# US 12,001,364 B2 · System for link management between multiple communication chips > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,001,364 B2 - Document ID: US12001364B2 - Status: Granted - Kind: B2 - Application number: 18/124,332 - Filed: 2023-03-21 - Published: 2023-07-13 - Granted: 2024-06-04 - Earliest claimed: 2020-01-03 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Helena Deirdre O'Shea; Camille Chen; Vijay Kumar Ramamurthi; Alon Paycher; Matthias Sauer; Bernd W. Adler - Web page: https://patentgrep.com/patent/US12001364B2 ## CPC - G06F 9/5011: {the resources being hardware resources other than CPUs, Servers and Terminals} - G06F 13/3625: {using a time dependent access} - G06F 11/3051: {Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs (verification or detection of system hardware configuration G06F11/2247)} - G06F 11/3409: {for performance assessment} - G06F 13/12: using hardware independent of the central processor, e.g. channel or peripheral processor - G06F 13/24: using interrupt (G06F13/32 takes precedence) - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F 13/4068: {Electrical coupling} - G06F 11/3055: {Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available (error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction of the data by redundancy in operations G06F11/14; error detection or correction by redundancy in hardware G06F11/16)} - G06F 2213/0038: System on Chip - G06F 2213/40: Bus coupling - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity. In response to determining that the other integrated circuit is authorized to execute the activity, the processor circuit sends, to the other integrated circuit over a configurable direct connection, an authorization signal authorizing the other integrated circuit to execute the activity. ## Claims ### Claim 1 A first integrated circuit, comprising: an interface circuit configured to communicate with a second integrated circuit over a multi-drop bus in an electronic device; and a processor circuit configured to: send a notify signal to a third integrated circuit over a first configurable direct connection separate from the multi-drop bus, the notify signal indicating assumed authorization for executing an activity at the first integrated circuit, receive a request from the second integrated circuit over a second configurable direct connection separate from the multi-drop bus, the request associated with timing information indicating a time when one or more resources become available for release by the first integrated circuit, and responsive to the received request, send a response to the second integrated circuit over the second configurable direct connection informing the second integrated circuit about the time when the one or more resources become available for release. ### Claim 2 (depends on 1) The first integrated circuit of claim 1, wherein the processor circuit is further configured to: perform, within a time limit, an internal arbitration to determine the time when the one or more resources become available for release; and send, within the time limit based on the internal arbitration, the response to the second integrated circuit over the second configurable direct connection. ### Claim 3 (depends on 1) The first integrated circuit of claim 1, wherein the processor circuit is further configured to: send, responsive to the received request, the response asynchronously to the second integrated circuit over the second configurable direct connection. ### Claim 4 (depends on 1) The first integrated circuit of claim 1, wherein: the interface circuit is further configured to communicate, with the second integrated circuit via the multi-drop bus, first data with a first latency; and the processor circuit is further configured to communicate, with the second integrated circuit over the second configurable direct connection, second data with a second latency that is less than the first latency. ### Claim 5 (depends on 1) The first integrated circuit of claim 1, wherein the processor circuit is further configured to: receive, from the second integrated circuit over the second configurable direct connection, a second request for a change in state of at least one resource shared by the first integrated circuit and the third integrated circuit; and trigger the change in state of the at least one shared resource in response to the received second request. ### Claim 6 (depends on 1) The first integrated circuit of claim 1, wherein the processor circuit is further configured to: receive, from the third integrated circuit over the first configurable direct connection, an external request signal; and generate an interrupt signal in response to the received external request signal. ### Claim 7 (depends on 6) The first integrated circuit of claim 6, wherein the processor circuit is further configured to: switch, responsive to the interrupt signal, one or more components of the first integrated circuit from an inactive state to an active state; and initiate a response for the third integrated circuit via the one or more components switched to the active state. ### Claim 8 (depends on 1) The first integrated circuit of claim 1, wherein the processor circuit is further configured to: receive, from the second integrated circuit over the second configurable direct connection, an interrupt signal; and generate a response to the received interrupt signal at a time when the first integrated circuit wakes up from a sleep state. ### Claim 9 (depends on 1) The first integrated circuit of claim 1, wherein the processor circuit is further configured to: receive, from the second integrated circuit over the second configurable direct connection, a request for an action at the first integrated circuit; and receive, from the third integrated circuit over the first configurable direct connection, information about a priority of the request for the action, and wherein the interface circuit is further configured to coordinate with one or more external devices over the multi-drop bus, in response to the request for the action and the information about the priority. ### Claim 10 A method of coordinating operations of electronic components in an electronic device at a first integrated circuit of the electronic device, the method comprising: communicating with a second integrated circuit over a multi-drop bus in the electronic device; sending a notify signal to a third integrated circuit over a first configurable direct connection separate from the multi-drop bus, the notify signal indicating assumed authorization for executing an activity at the first integrated circuit; receiving a request from the second integrated circuit over a second configurable direct connection separate from the multi-drop bus, the request associated with timing information indicating a time when one or more resources become available for release by the first integrated circuit; and responsive to the received request, sending a response to the second integrated circuit over the second configurable direct connection informing the second integrated circuit about the time when the one or more resources become available for release. ### Claim 11 (depends on 10) The method of claim 10, further comprising: performing, within a time limit, an internal arbitration to determine the time when the one or more resources become available for release; and sending, within the time limit based on the internal arbitration, the response to the second integrated circuit over the second configurable direct connection. ### Claim 12 (depends on 10) The method of claim 10, further comprising: sending, responsive to the received request, the response asynchronously to the second integrated circuit over the second configurable direct connection. ### Claim 13 (depends on 10) The method of claim 10, further comprising: communicating, with the second integrated circuit via the multi-drop bus, first data with a first latency; and communicating, with the second integrated circuit over the second configurable direct connection, second data with a second latency that is less than the first latency. ### Claim 14 (depends on 10) The method of claim 10, further comprising: receiving, from the second integrated circuit over the second configurable direct connection, a second request for a change in state of at least one resource shared by the first integrated circuit and the third integrated circuit; and triggering the change in state of the at least one shared resource in response to the received second request. ### Claim 15 (depends on 10) The method of claim 10, further comprising: receiving, from the third integrated circuit over the first configurable direct connection, an external request signal; and generating an interrupt signal in response to the received external request signal. ### Claim 16 (depends on 15) The method of claim 15, further comprising: switching, responsive to the interrupt signal, one or more components of the first integrated circuit from an inactive state to an active state; and initiating a response for the third integrated circuit via the one or more components switched to the active state. ### Claim 17 (depends on 10) The method of claim 10, further comprising: receiving, from the second integrated circuit over the second configurable direct connection, an interrupt signal; and generating a response to the received interrupt signal at a time when the first integrated circuit wakes up from a sleep state. ### Claim 18 (depends on 10) The method of claim 10, further comprising: receiving, from the second integrated circuit over the second configurable direct connection, a request for an action at the first integrated circuit; receiving, from the third integrated circuit over the first configurable direct connection, information about a priority of the request for the action; and coordinating with one or more external devices over the multi-drop bus, in response to the request for the action and the information about the priority. ### Claim 19 An electronic device, comprising: a multi-drop bus; and a first integrated circuit connected to a second integrated circuit via the multi-drop bus and to a third integrated circuit via a first configurable direct connection separate from the multi-drop bus, the first integrated circuit configured to: send a notify signal to the third integrated circuit over the first configurable direct connection, the notify signal indicating assumed authorization for executing an activity at the first integrated circuit, receive a request from the second integrated circuit over a second configurable direct connection separate from the multi-drop bus, the request associated with timing information indicating a time when one or more resources become available for release by the first integrated circuit, and responsive to the received request, send a response to the second integrated circuit over the second configurable direct connection informing the second integrated circuit about the time when the one or more resources become available for release. ### Claim 20 (depends on 19) The electronic device of claim 19, wherein the first integrated circuit is further configured to: communicate, with the second integrated circuit via the multi-drop bus, first data with a first latency; and communicate, with the second integrated circuit over the second configurable direct connection, second data with a second latency that is less than the first latency.