# US 12,001,362 B2 · Dynamically reprogrammable topologically unique integrated circuit identification > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,001,362 B2 - Document ID: US12001362B2 - Status: Granted - Kind: B2 - Application number: 17/394,536 - Filed: 2021-08-05 - Published: 2022-02-17 - Granted: 2024-06-04 - Earliest claimed: 2020-08-17 - Assignees: Nokia Technologies Oy - Applicants: Nokia Technologies Oy - Inventors: Shahriar Shahramian; David Skoglund - Web page: https://patentgrep.com/patent/US12001362B2 ## CPC - G06F 13/36: for access to common bus or bus system - G06F 13/4247: {on a daisy chain bus} - G06F 1/10: Distribution of clock signals {, e.g. skew} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method, apparatus, and computer program product provide for dynamically reprogrammable topologically unique integrated circuit identification. In an example embodiment, an integrated circuit may be arranged among multiple integrated circuits. The integrated circuit may be configured to derive a topologically unique identifier by performing input measurements of stimuli provided by a host circuit. The integrated circuit may be topologically indistinguishable from at least one other integrated circuit of the multiple integrated circuits from a perspective of the host circuit. ## Claims ### Claim 1 An integrated circuit arranged among a plurality of integrated circuits, the integrated circuit comprising: an identification circuit configured to derive a topologically unique identifier by performing an input measurement of a stimulus provided by a host circuit, wherein the topologically unique identifier is set using a plurality of pull values that are arranged such that no repeated sequence of pull values exists in a detectable chain of pull values associated with other integrated circuits within the plurality of integrated circuits, wherein the integrated circuit is topologically indistinguishable from at least one other integrated circuit of the plurality of integrated circuits from a perspective of the host circuit, wherein the integrated circuit and the other integrated circuits within the plurality of integrated circuits are communicably coupled with the host circuit via a shared communication bus, wherein the input measurement comprises a binary input measurement or a non-binary input measurement based on one or more values comprising one or more of a pin voltage, a supply voltage, or a pin logic level of the integrated circuit, and wherein, responsive to resetting or powering on the integrated circuit, the identification circuit is further configured to receive topologically unique data from the host circuit. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the plurality of integrated circuits is arranged as an array, a cluster, a single dimension cluster, a multi-dimensional cluster, or an array comprising one or more clusters. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein the identification circuit is further configured to perform the input measurement based on a command received from the host circuit. ### Claim 4 (depends on 1) The integrated circuit of claim 1, wherein performing a non-binary input measurement comprises one or more of detecting an input measurement value relative to a host command and a prior input measurement, detecting an input measurement value relative to one or more thresholds, or detecting an input measurement value delay relative to a clock. ### Claim 5 (depends on 1) The integrated circuit of claim 1, wherein the identification circuit is further configured to assert an output based at least in part on a command received from the host circuit. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein the plurality of integrated circuits is arranged according to a chain such that a first output pin of the integrated circuit is communicably coupled with a second input pin of a second integrated circuit and a second output pin of the second integrated circuit is communicably coupled with a third input pin of a third integrated circuit. ### Claim 7 (depends on 6) The integrated circuit of claim 6, wherein the identification circuit is further configured to: receive, from the host circuit, a head of chain command; and set a chain input enable bit of the identification circuit. ### Claim 8 (depends on 7) The integrated circuit of claim 7, wherein a first input pin of the integrated circuit is communicably coupled with the host circuit via the shared communication bus. ### Claim 9 (depends on 8) The integrated circuit of claim 8, wherein the identification circuit is further configured to: detect that a chain input enable bit is set; and propagate a value of the first input of the integrated circuit to the first output of the integrated circuit. ### Claim 10 (depends on 6) The integrated circuit of claim 6, wherein at least one stimulus is shared among two or more integrated circuits of the plurality of integrated circuits. ### Claim 11 (depends on 10) The integrated circuit of claim 10, wherein the at least one stimulus is generated uniquely in the chain such that faults in the chain are recoverable. ### Claim 12 (depends on 1) The integrated circuit of claim 1, wherein the identification circuit is further configured to receive the unique identifier via one or more pins, inputs, or outputs associated with a functional circuit of the integrated circuit. ### Claim 13 (depends on 1) The integrated circuit of claim 1, wherein the integrated circuit is addressable by the host circuit using the topologically unique identifier. ### Claim 14 (depends on 1) The integrated circuit of claim 1, wherein the identification circuit is further configured to receive a subsequent topologically unique identifier from the host circuit. ### Claim 15 (depends on 14) The integrated circuit of claim 14, wherein the integrated circuit is addressable by the host circuit using the subsequent topologically unique identifier. ### Claim 16 (depends on 1) The integrated circuit of claim 1, wherein the identification circuit is further configured to modify integrated circuit features based on a location of the integrated circuit within a topology of the plurality of integrated circuits. ### Claim 17 (depends on 1) The integrated circuit of claim 1, wherein the identification circuit is further configured to execute a broadcast command received from the host circuit or one or more other integrated circuits. ### Claim 18 (depends on 17) The integrated circuit of claim 17, wherein executing the broadcast command comprises decoding a first broadcast ID of the broadcast command. ### Claim 19 (depends on 18) The integrated circuit of claim 18, wherein executing the broadcast command further comprises executing an action associated with the command when a second broadcast ID of the integrated circuit matches the first broadcast ID of the broadcast command. ### Claim 20 (depends on 1) The integrated circuit of claim 1, wherein the topologically unique data comprises one or more of: customer identification data for programmatic customization of bus communication, customer identification data for modifying, enabling, or disabling one or more features associated with the integrated circuit, data for modifying one or more features associated with the integrated circuit based on a location of the integrated circuit within the plurality of integrated circuits, or data for modifying one or more features associated with the integrated circuit in the event that damage occurs to the host circuit.