# US 12,001,360 B2 · Data transmission method and electronic chip of the manycore type

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- Number: US 12,001,360 B2
- Document ID: US12001360B2
- Status: Granted
- Kind: B2
- Application number: 17/798,249
- Filed: 2021-02-03
- Published: 2023-03-09
- Granted: 2024-06-04
- Earliest claimed: 2020-02-14
- Assignees: Safran Electronics & Defense
- Applicants: Safran Electronics & Defense
- Inventors: Louis-Théophile Thirion; Sangeerthman Subramaniam; Nicolas Maitrot; Jean-Charles Riand
- Web page: https://patentgrep.com/patent/US12001360B2

## CPC

- G06F 11/2007: {using redundant communication media}
- G06F 13/225: {with priority control}
- G06F 11/2012: {and using different communication protocols}
- G06F 11/2041: {with more than one idle spare processing component}
- G06F 11/2043: {where the redundant components share a common memory address space}
- G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus}
- G06F 15/7825: {Globally asynchronous, locally synchronous, e.g. network on chip}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method for transmitting data between functions implemented on a first electronic chip of the manycore type. The first electronic chip includes a plurality of execution cores, the execution cores being grouped in clusters, the clusters being interconnected by at least two communication systems. The data transmission method includes the steps of: implementing a first function on a first cluster; implementing a second function on a second cluster, characterised in that the second function is also implemented on a third cluster distinct from the first and second clusters; and transmitting at least one data item between the first function and the second function.

## Claims

### Claim 1

A method for transmitting data between functions implemented on a first electronic chip of the manycore type comprising a plurality of execution cores, said execution cores being grouped in a cluster, a plurality of clusters (C0 to C4) being interconnected by at least one first communication system and a second communication system different from said first communication system, wherein said method causes the first electronic chip to perform:
implementing a first function (A) on a first cluster (C1);
implementing a second function (B) on a second cluster (C2), wherein said second function (B′) is also implemented on a third cluster (C3) distinct from said first and second cluster; and
transmitting at least one data item between said first function and said second function, implemented on the second cluster and said second function implemented on the third cluster both through said first communication system and through said second communication system so that in the event that said first communication system fails, the second function (B′) implemented on the third cluster (C3) will still receive the at least one data item through said second communication system.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the first communication system comprises a first communication link (L1) and the second communication system comprises a second communication link (L2), and wherein transmitting at least one data item between said first function and said second function comprises transmitting a data item between said first function and said second function both on the first communication link belonging to the first communication system and on the second communication link belonging to the second communication system.

### Claim 3 (depends on 1)

The method according to claim 1, wherein, one of said communication systems having priority, in the case of a plurality of receptions of said data item by said second function implemented on said second cluster only the data item received through said priority communication system is kept and in the case of a plurality of receptions of said data item by said second function implemented on said third cluster only the data item received through said priority communication system is kept.

### Claim 4 (depends on 1)

The method according to claim 1, wherein said first communication system is of the network on a chip type.

### Claim 5 (depends on 1)

The method according to claim 1, wherein said second communication system is a parallel bus.

### Claim 6 (depends on 1)

The method according to claim 1, wherein, said first electronic chip being interconnected to a second electronic chip of the manycore type distinct from said first electronic chip, said first function is furthermore implemented on a first cluster of said second electronic chip and said second function is furthermore implemented on a second cluster of said second electronic chip.

### Claim 7 (depends on 6)

The method according to claim 6, wherein said first function implemented on one of said first or second chips transmits at least one data item to said second function implemented on the other of said first or second chips both on a first communication link of the network on a chip type and on a second communication link of the parallel bus type.

### Claim 8 (depends on 1)

The method according to claim 1, wherein, said first electronic chip being interconnected to a third electronic chip of the multicore type, said first function is furthermore implemented on a first core of said third electronic chip and said second function is furthermore implemented on a second core of said third electronic chip.

### Claim 9 (depends on 8)

The method according to claim 8, wherein said first function implemented on one of said first or second chips transmits at least one data item to said second function implemented on the other one of said first or second chips both on a first communication link of the Ethernet type (Lc) and on a second communication link of the PCIe type.

### Claim 10

An electronic chip of the manycore type comprising a plurality of execution cores, said execution cores being grouped in clusters, said clusters (C0 to C4) being interconnected by at least one first communication system and a second communication system different from said first communication system, the electronic chip comprising:
first cluster (C1) on which a first function (A) is implemented;
second cluster (C2) on which a second function (B) is implemented;
a third cluster (C3) on which said second function (B′) is implemented, said third cluster being distinct from said first and second clusters; and
communication links between said first cluster and said second and third clusters configured for transmitting at least one data item between said first function and said second function implemented on the second cluster and said second function implemented on the third cluster both through said first communication system and through said second communication system so that in the event that said first communication system fail, the second function (B′) implemented on the third cluster (C3) will still receive that at least one data item through said second communication system.

### Claim 11 (depends on 10)

A system comprising a first electronic chip according to claim 10 interconnected to a second electronic chip of the manycore type distinct from said first electronic chip, wherein said first function is furthermore implemented on a first cluster of said second electronic chip and said second function is furthermore implemented on a second cluster of said second electronic chip.

### Claim 12 (depends on 10)

A system comprising a first electronic chip according to claim 10 interconnected to a third electronic chip of the multicore type distinct from said first electronic chip, wherein said first function is furthermore implemented on a first core of said third electronic chip and said second function is furthermore implemented on a second core of said third electronic chip.

### Claim 13 (depends on 11)

The system according to claim 11, wherein said first communication system is of the network on a chip type.

### Claim 14 (depends on 11)

The system according to claim 11, wherein said second communication system is a parallel bus.