# US 12,001,357 B2 · Direct memory access circuit, microcontroller, and method of controlling a direct memory access > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,001,357 B2 - Document ID: US12001357B2 - Status: Granted - Kind: B2 - Application number: 17/686,445 - Filed: 2022-03-04 - Published: 2023-09-07 - Granted: 2024-06-04 - Earliest claimed: 2022-03-04 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Frank Hellwig; Sandeep Vangipuram - Web page: https://patentgrep.com/patent/US12001357B2 ## CPC - G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)} - G06F 9/5016: {the resource being the memory} - G06F 13/1621: {by maintaining request order} - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F 13/30: with priority control - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A direct memory access (DMA) circuit is provided. The DMA circuit may include a plurality of groups of direct memory access channels, wherein each of the groups includes at least one DMA channel and a resource usage counter configured to count an execution time in which one of the DMA channels of the group is executed, and an arbiter configured to evaluate a value of the resource usage counter of a group upon a request for execution time by one of the DMA channels of the group, and, taking into account a result of the evaluation, to assign, delay assignment, or deny execution time for using the direct memory access to one of the groups. ## Claims ### Claim 1 A direct memory access (DMA) circuit, comprising: a plurality of groups of direct memory access channels, wherein each of the groups comprises at least one DMA channel and a resource usage counter configured to count an execution time in which one of the DMA channels of the group is executed; and an arbiter configured to evaluate a value of the resource usage counter of a group upon a request for execution time by one of the DMA channels of the group, and, taking into account a result of the evaluation, to assign, delay assignment, or deny execution time for using the direct memory access to one of the groups. ### Claim 2 (depends on 1) The DMA circuit of claim 1, wherein the evaluating comprises comparing the value with a predefined threshold value. ### Claim 3 (depends on 2) The DMA circuit of claim 2, wherein the DMA circuit is further configured to reset the resource usage counter for each of the groups after a predefined time interval, and wherein the predefined time interval is larger than a time span defined by the predefined threshold value. ### Claim 4 (depends on 3) The DMA circuit of claim 3, further comprising: a memory element; wherein the DMA circuit is configured to store the value of each of the groups in the memory element before the reset of the resource usage counter. ### Claim 5 (depends on 3) The DMA circuit of claim 3, wherein the DMA circuit is further configured to analyze the stored values of each of the groups and/or to provide the stored values to a processor for analysis, and to adjust the threshold value and/or a reset value of the resource usage counter in accordance with a result of the analysis. ### Claim 6 (depends on 1) The DMA circuit of claim 1, wherein each group further comprises a delay time counter configured to start counting when delaying execution time; and wherein the arbiter is further configured to compare a value of the delay time counter of the group with a predefined second threshold value, and, if the value is identical to or exceeds the second predefined threshold value, to assign the execution time to the group. ### Claim 7 (depends on 3) The DMA circuit of claim 3, further comprising a register and a storage mode indicator; wherein the register is configured as the resource usage counter until the value of the resource usage indicator reaches the threshold value; wherein the register is configured as the delay time counter after the value of the resource usage indicator has reached the threshold value; and wherein the storage mode indicator is configured to indicate whether the register is presently configured as the resource usage counter or as the delay time counter. ### Claim 8 (depends on 1) The DMA circuit of claim 1, wherein the resource usage counter is configured as a register. ### Claim 9 A method of controlling a direct memory access (DMA) circuit comprising a plurality of groups of direct memory access channels, wherein each of the groups comprises at least one DMA channel, the method comprising: counting an execution time in which one of the DMA channels of the group is executed; evaluating the counted execution time of a group upon a request for execution time by one of the DMA channels of the group; and taking into account a result of the evaluation, assigning, delaying assignment, or denying execution time for using the direct memory access to one of the groups. ### Claim 10 (depends on 9) The method of claim 9, wherein the evaluating comprises comparing the value with a predefined threshold value. ### Claim 11 (depends on 10) The method of claim 10, wherein each group further comprises a delay time counter; the method further comprising: for the delaying the assigning of execution time to the group, comparing a value of the delay time counter of the first ranked group with a predefined second threshold value, and, if the value is identical to or exceeds the second predefined threshold value, assigning the execution time to the group. ### Claim 12 (depends on 11) The method of claim 11, wherein the DMA circuit further comprises a register and a storage mode indicator; wherein the register is configured for storing the counted resource usage until the value of the resource usage indicator reaches the threshold value; and wherein the register is configured to store the counted delay time after the value of the resource usage indicator has reached the threshold value; and indicating, using the storage mode indicator, whether the register is presently configured as the resource usage counter or as the delay time counter. ### Claim 13 (depends on 10) The method of claim 10, further comprising: individually preconfiguring the second threshold value for each of the groups. ### Claim 14 (depends on 10) The method of claim 10, further comprising: individually preconfiguring the threshold value for each of the groups. ### Claim 15 (depends on 10) The method of claim 10, further comprising: resetting the resource usage counter for each of the groups after a predefined time interval, wherein the predefined time interval is larger than a time span defined by the predefined threshold value. ### Claim 16 (depends on 15) The method of claim 15, wherein the DMA circuit further comprises a memory element, the method further comprising: storing the value of the resource usage of each of the groups in the memory element before resetting the resource usage counter. ### Claim 17 (depends on 16) The method of claim 16, further comprising: analyzing the stored values of each of the groups; and adjusting the threshold value and/or a reset value of the resource usage counter in accordance with a result of the analysis. ### Claim 18 A direct memory access (DMA) circuit, comprising: a plurality of groups of direct memory access channels, wherein each of the groups comprises at least one DMA channel and a resource usage determination circuit configured to determine an execution time in which a respective one of the DMA channels of the group is executed; and an arbiter configured to assign, delay assignment, or deny execution time for using the direct memory access to one of the groups based on an indication of the resource usage determination circuit. ### Claim 19 (depends on 18) The DMA circuit of claim 18, wherein the indication of the resource usage determination circuit includes an indication if the group has exceeded a predefined resource usage threshold value. ### Claim 20 (depends on 18) The DMA circuit of claim 18, wherein the arbiter is configured to evaluate based on the indication of the resource usage determination circuit if the group has exceeded a predefined resource usage threshold value.