# US 12,001,354 B2 · Semiconductor device and method

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- Number: US 12,001,354 B2
- Document ID: US12001354B2
- Status: Granted
- Kind: B2
- Application number: 17/991,914
- Filed: 2022-11-22
- Published: 2023-03-16
- Granted: 2024-06-04
- Earliest claimed: 2020-09-16
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Tomoaki Suzuki
- Web page: https://patentgrep.com/patent/US12001354B2

## CPC

- G06F 13/1668: {Details of memory controller}
- G06F 12/0284: {Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163)}
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 2212/1024: Latency reduction
- G06F 2212/502: using adaptive policy
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices
- G11C 7/1009: {Data masking during input/output}
- G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 16/06: Auxiliary circuits, e.g. for writing into memory
- G11C 2207/2245: Memory devices with an internal cache buffer
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A semiconductor device includes a terminal group configured to receive a first signal and a second signal from a host, a first chip electrically connected to the terminal group, and a second chip electrically connected to the terminal group. The first chip is configured to, in response to reception of the first signal, transmit a third signal corresponding to the first signal to the second chip. The first chip is configured to, when the first chip has received the second signal before the first signal, refrain from transmitting the third signal to the second chip.

## Claims

### Claim 1

A semiconductor device comprising:
a terminal group configured to receive a first signal and a second signal from a host;
a first chip electrically connected to the terminal group and configured to receive the first signal and the second signal; and
a second chip electrically connected to the first chip and configured to receive a third signal from the first chip, the third signal corresponding to the first signal,
wherein the first chip is configured to:
transmit the third signal to the second chip by the first chip receiving the first signal, and
refrain from transmitting the third signal to the second chip by the first chip receiving the second signal before the first chip receiving the first signal.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
the terminal group includes a dedicated terminal for receiving the second signal.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein
the second signal includes a first command transmitted from the host via a terminal that transmits the first signal.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, wherein
the second chip is configured to, in spite of reception of the first command, refrain from responding to the first command.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein
the first chip includes a first memory,
the second chip includes a second memory,
the first signal includes a command for writing first information into the first memory or the second memory, and
the first chip is configured to store the first information into the first memory, in response to reception of the second signal before the command.

### Claim 6 (depends on 2)

The semiconductor device according to claim 2, wherein
the first chip includes a first memory,
the second chip includes a second memory,
the first signal includes a second command for writing first information into the first memory or the second memory, and
the first chip is configured to store the first information into the first memory, in response to reception of the second signal before the second command.

### Claim 7 (depends on 3)

The semiconductor device according to claim 3, wherein
the first chip includes a first memory,
the second chip includes a second memory,
the first signal includes a second command for writing first information into the first memory or the second memory, and
the first chip is configured to store the first information into the first memory, in response to reception of the second signal before the second command.

### Claim 8 (depends on 4)

The semiconductor device according to claim 4, wherein
the first chip includes a first memory,
the second chip includes a second memory,
the first signal includes a second command for writing first information into the first memory or the second memory, and
the first chip is configured to store the first information into the first memory, in response to reception of the second signal before the second command.

### Claim 9 (depends on 5)

The semiconductor device according to claim 5, wherein
the second chip comprises a third memory, and
the first information includes second information representing a set value of a size of data to be input or output to or from the third memory.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, wherein
the first signal includes a third command for causing the second chip to output data from the third memory,
the first chip includes a fourth memory, and
the first chip is configured to:
transmit a fourth command corresponding to the first signal to the second chip, in response to reception of the first signal after receiving the third command from the host;
sequentially buffer first data in the fourth memory, the first data being data output from the second chip in accordance with the fourth command; and
notify the host of third information representing that a size of the first data buffered in the fourth memory has reached a threshold, the threshold being defined based on the second information.

### Claim 11 (depends on 10)

The semiconductor device according to claim 10, wherein
the first chip is configured to start supplying the first data from the fourth memory to the host after allowing notification of the third information.

### Claim 12 (depends on 10)

The semiconductor device according to claim 10, wherein
when a data transfer rate between the host and the first chip is N times higher than a data transfer rate between the first chip and the second chip, where N is larger than one, the threshold is calculated by multiplying a data size indicated by the second information by (1−1/N).

### Claim 13 (depends on 1)

The semiconductor device according to claim 1, wherein
the first chip is configured to switch between a first mode and a second mode by the first chip receiving the second signal,
the first mode transmits the third signal corresponding to the first signal to the second chip, and
the second mode refrains from transmitting the third signal to the second chip by the first chip receiving the second signal before the first chip receives the first signal.

### Claim 14

A method of controlling a first chip electrically connected to a second chip, the method comprising:
transmitting a second signal corresponding to a first signal to the second chip by the first chip receiving the first signal from a host; and
refraining from transmitting the second signal to the second chip by the first chip receiving a third signal before the first chip receives the first signal.

### Claim 15 (depends on 14)

The method according to claim 14, wherein
the first chip includes a first memory,
the second chip includes a second memory, and
the first signal includes a first command for writing first information into the first memory or the second memory, the method further comprising
storing the first information into the first memory, in response to reception of the third signal before the first command.

### Claim 16 (depends on 15)

The method according to claim 15, wherein
the second chip includes a third memory, and
the first information includes second information representing a set value of a size of data to be input or output to or from the third memory.

### Claim 17 (depends on 16)

The method according to claim 16, wherein
the first signal includes a second command for causing the second chip to output data from the third memory, and
the first chip comprises a fourth memory, the method further comprising:
transmitting a third command corresponding to the first signal to the second chip, in response to reception of the first signal after receiving the second command from the host;
sequentially buffering first data in a fourth memory, the first data being data output from the second chip in accordance with the third command; and
transferring, to the host, third information representing that a size of the first data buffered in the fourth memory has reached a threshold, the threshold being defined based on the second information.

### Claim 18 (depends on 17)

The method according to claim 17, further comprising
starting supply of the first data from the fourth memory to the host after the size of the first data buffered in the fourth memory has reached the threshold.

### Claim 19 (depends on 17)

The method according to claim 17, further comprising
when a data transfer rate between the host and the first chip is N times higher than a data transfer rate between the first chip and the second chip, where N is larger than one, calculating the threshold by multiplying a data size indicated by the second information by (1−1/N).

### Claim 20

A semiconductor device comprising:
a terminal group configured to receive a first signal and a second signal from a host;
a first chip electrically connected to the terminal group and configured to receive the first signal and the second signal; and
a second chip electrically connected to the first chip and configured to receive a third signal from the first chip, the third signal corresponding to the first signal, wherein
the first chip is configured to switch between a first mode and a second mode by the first chip receiving the second signal,
the first mode transmits a third signal corresponding to the first signal to the second chip, and
the second mode refrains from transmitting the third signal to the second chip by the first chip receiving the second signal before the first chip receives the first signal.