# US 12,001,351 B2 · Multiple-requestor memory access pipeline and arbiter

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- Number: US 12,001,351 B2
- Document ID: US12001351B2
- Status: Granted
- Kind: B2
- Application number: 17/734,174
- Filed: 2022-05-02
- Published: 2022-08-18
- Granted: 2024-06-04
- Earliest claimed: 2019-05-24
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Abhijeet Ashok Chachad; David Matthew Thompson
- Web page: https://patentgrep.com/patent/US12001351B2

## CPC

- G06F 13/1605: {based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36)}
- G06F 12/08: in hierarchically structured memory systems, e.g. virtual memory systems
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In described examples, a coherent memory system includes a central processing unit (CPU) and first and second level caches. The memory system can include a pipeline for accessing data stored in one of the caches. Requestors can access the data stored in one of the caches by sending requests at a same time that can be arbitrated by the pipeline.

## Claims

### Claim 1

A device comprising:
a set of requestors configured to provide a set of memory transaction requests;
a first set of arbitration units that includes a respective arbitration unit coupled to each requestor of the set of requestors;
a cache memory that includes a set of memory banks; and
a pipeline circuit coupled between the first set of arbitration units and the cache memory that includes a set of parallel pipelines that includes a respective pipeline associated with each memory bank of the set of memory banks, wherein:
each pipeline of the set of parallel pipelines includes a respective arbitration unit of a second set of arbitration units; and
the first set of arbitration units and the second set of arbitration units are coupled to perform, on each memory transaction request of the set of memory transaction requests, a first arbitration using the first set of arbitration units and a second arbitration using the second set of arbitration units.

### Claim 2 (depends on 1)

The device of claim 1, wherein:
the first arbitration is among a first subset of the set of memory transaction requests associated with a requestor of the set of requestors; and
the second arbitration is among a second subset of the set of memory transaction requests associated with a memory bank of the set of memory banks.

### Claim 3 (depends on 1)

The device of claim 1, wherein the first arbitration is based on whether a request of the set of memory transaction requests is blocking or non-blocking.

### Claim 4 (depends on 1)

The device of claim 1, wherein the second arbitration is based on at least one of: address hazard avoidance; structural hazard avoidance; pipeline hazard avoidance; or reservation credit count.

### Claim 5 (depends on 1)

The device of claim 1, wherein each pipeline of the set of parallel pipelines includes a respective arbitration unit of a third set of arbitration units coupled between the respective arbitration unit of the second set of arbitration units and the respective memory bank of the set of memory banks.

### Claim 6 (depends on 5)

The device of claim 5 further comprising a set of registers configured to store a set of priorities, wherein the third set of arbitration units is configured to perform a third arbitration on each memory transaction request of the set of memory transaction requests based on the set of priorities.

### Claim 7 (depends on 6)

The device of claim 6, wherein each priority of the set of priorities is associated with a respective requestor of the set of requestors.

### Claim 8 (depends on 1)

The device of claim 1 further comprising a set of first-in first-out (FIFO) buffers coupled between the set of requestors and the first set of arbitration units, wherein each FIFO buffer of the set of FIFO buffers is associated with a transaction type.

### Claim 9 (depends on 1)

The device of claim 1, wherein the set of requestors includes at least one of: a program memory controller, a data memory controller, a vector memory controller, a multi-core shared memory controller, or a memory management unit.

### Claim 10 (depends on 1)

The device of claim 1, wherein the cache memory is a level two (L2) cache memory.

### Claim 11

A device comprising:
a set of cores;
a set of level one (L1) caches coupled to the set of cores;
a set of requestors that includes a set of memory controllers coupled to the set of L1 caches;
a level two (L2) cache controller coupled to the set of requestors; and
an L2 memory coupled to the L2 cache controller that includes a set of banks, wherein the L2 cache controller includes:
a first set of arbitration units that includes a respective arbitration unit coupled to each requestor of the set of requestors; and
a pipeline circuit coupled to the first set of arbitration units that includes a set of parallel pipelines that includes a respective pipeline associated with each memory bank of the set of memory banks, wherein each pipeline of the set of parallel pipelines includes a respective arbitration unit of a second set of arbitration units.

### Claim 12 (depends on 11)

The device of claim 11, wherein:
the first set of arbitration units is configured to perform a first arbitration among a first subset of the set of memory transaction requests associated with a requestor of the set of requestors; and
the second set of arbitration units is configured to perform a second arbitration among a second subset of the set of memory transaction requests associated with a memory bank of the set of memory banks.

### Claim 13 (depends on 11)

The device of claim 11, wherein each pipeline of the set of parallel pipelines includes a respective arbitration unit of a third set of arbitration units coupled between the respective arbitration unit of the second set of arbitration units and the respective memory bank of the set of memory banks.

### Claim 14

A method comprising:
receiving a set of memory transaction requests from a set of requestors, wherein the set of memory transaction requests are directed to a cache memory that includes a set of memory banks;
performing, by a first set of arbitration units, a first arbitration on the set of memory transaction requests among subsets of the set of memory transaction requests each associated with a respective requestor of the set of requestors;
performing, by a second set of arbitration units, a second arbitration on the set of memory transaction requests among subsets of the set of memory transaction requests each associated with a respective memory bank of the set of memory banks; and
thereafter, servicing the set of memory transaction requests using the cache memory.

### Claim 15 (depends on 14)

The method of claim 14, wherein the first arbitration is based on whether a request of the set of memory transaction requests is blocking or non-blocking.

### Claim 16 (depends on 14)

The method of claim 14, wherein the second arbitration is based on at least one of: address hazard avoidance; structural hazard avoidance; pipeline hazard avoidance; or reservation credit count.

### Claim 17 (depends on 14)

The method of claim 14 further comprising, after the performing of the second arbitration and prior to the servicing of the set of memory transaction requests, performing, by a third set of arbitration units, a third arbitration on the set of memory transaction requests.

### Claim 18 (depends on 17)

The method of claim 17 further comprising receiving a set of priorities, wherein the third arbitration is based on the set of priorities.

### Claim 19 (depends on 18)

The method of claim 18, wherein each priority of the set of priorities is associated with a respective requestor of the set of requestors.

### Claim 20 (depends on 14)

The method of claim 14, wherein the cache memory is a level two (L2) cache memory.