# US 12,001,345 B2 · Victim cache that supports draining write-miss entries

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- Number: US 12,001,345 B2
- Document ID: US12001345B2
- Status: Granted
- Kind: B2
- Application number: 18/340,944
- Filed: 2023-06-26
- Published: 2023-10-26
- Granted: 2024-06-04
- Earliest claimed: 2019-05-24
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Naveen Bhoria; Timothy David Anderson; Pete Hippleheuser
- Web page: https://patentgrep.com/patent/US12001345B2

## CPC

- G06F 12/128: adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
- G06F 9/3001: {Arithmetic instructions}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/546: {Message passing systems or structures, e.g. queues}
- G06F 11/1064: {in cache or content addressable memories}
- G06F 12/0215: {with look ahead addressing means}
- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)}
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 12/0804: with main memory updating (G06F12/0806 takes precedence)
- G06F 12/0806: Multiuser, multiprocessor or multiprocessing cache systems
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0815: Cache consistency protocols
- G06F 12/082: {Associative directories (G06F12/0822 takes precedence)}
- G06F 12/0853: Cache with multiport tag or data arrays
- G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
- G06F 12/0864: using pseudo-associative means, e.g. set-associative or hashing
- G06F 12/0884: Parallel mode, e.g. in parallel with main memory or CPU
- G06F 12/0888: using selective caching, e.g. bypass
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/0895: of parts of caches, e.g. directory or tag array
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 12/12: Replacement control
- G06F 12/121: using replacement algorithms
- G06F 12/126: with special data handling, e.g. priority of data or instructions, handling errors or pinning
- G06F 12/127: using additional replacement algorithms
- G06F 13/1605: {based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36)}
- G06F 13/1642: {with request queuing}
- G06F 13/1673: {using buffers}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F 15/8069: {using a cache}
- G11C 5/066: {Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/1015: {Read-write modes for single port memories, i.e. having either a random port or a serial port}
- G11C 7/106: {Data output latches}
- G11C 7/1075: {for multiport memories each having random access ports and serial ports, e.g. video RAM}
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- G11C 7/1087: {Data input latches}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 29/72: {with optimized replacement algorithms}
- G11C 29/76: {using address translation or modifications}
- G06F 2212/1016: Performance improvement
- G06F 2212/1021: Hit rate improvement
- G06F 2212/1024: Latency reduction
- G06F 2212/1041: Resource optimization
- G06F 2212/1044: Space efficiency improvement
- G06F 2212/301: In special purpose processing node, e.g. vector processor
- G06F 2212/454: Vector or matrix data
- G06F 2212/603: of operating mode, e.g. cache mode or local memory mode
- G06F 2212/6032: Way prediction in set-associative cache
- G06F 2212/6042: Allocation of cache space to multiple users or processors
- G06F 2212/608: Details relating to cache mapping
- G06F 2212/62: Details of cache specific to multiprocessor cache arrangements
- G11C 29/4401: {for self repair}
- G11C 2029/0409: {Online test}
- G11C 2029/0411: {Online error correction}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.

## Claims

### Claim 1

A device comprising:
a processor; and
a cache that includes:
a processor interface coupled to the processor;
a cache memory that includes:
a set of cache lines that includes a first cache line configurable to store a first write-miss entry; and
a set of line type entries that are each configured to store a respective value that specifies whether a respective line of the set of cache lines is associated with a write-miss entry; and
a controller coupled to the processor interface and to the cache memory and configured to:
detect a state of the processor interface; and
based on the state:
select the first cache line to evict based on the set of line type entries; and
evict the first cache line by providing a packet based on the first write-miss entry stored in the first cache line.

### Claim 2 (depends on 1)

The device of claim 1, wherein:
the cache includes a tag RAM; and
the controller is configured to select the first cache line to evict by walking the tag RAM.

### Claim 3 (depends on 1)

The device of claim 1, wherein the controller is configured to select the first cache line based on a first-in-first-out policy.

### Claim 4 (depends on 1)

The device of claim 1, wherein the controller is configured to select the first cache line based on a least recently used policy.

### Claim 5 (depends on 1)

The device of claim 1, wherein the controller is configured to select the first cache line based on a random selection policy.

### Claim 6 (depends on 1)

The device of claim 1, wherein:
the cache includes a drain buffer; and
the controller is configured to evict the first cache line by storing the packet in the drain buffer until an acknowledgment is received.

### Claim 7 (depends on 6)

The device of claim 6, wherein:
the cache is a first cache;
the device further comprises a second cache coupled to the processor;
the controller is configured to provide the packet to the second cache; and
the second cache is configured to provide the acknowledgment.

### Claim 8 (depends on 1)

The device of claim 1, wherein:
the cache memory is a victim cache memory; and
the set of line type entries each specify whether the respective line of the set of cache lines is associated with a write-miss entry or a victim cache entry.

### Claim 9 (depends on 1)

The device of claim 1, wherein the state is an idle state.

### Claim 10 (depends on 9)

The device of claim 9, wherein the controller is configured to select the first cache line to evict based on the processor interface being in the idle state for a number of clock cycles.

### Claim 11

A device comprising:
an interface;
a cache memory that includes a set of cache lines that are each configurable to store either a first type of entry or a second type of entry, wherein:
the second type of entry is a write-miss entry; and
the set of cache lines includes a first cache line configurable to store a first write-miss entry; and
a cache controller coupled to the interface and to the cache memory and configured to:
detect a state of the interface; and
based on the state:
select the first cache line to evict; and
evict the first cache line by providing a packet based on the first write-miss entry stored in the first cache line.

### Claim 12 (depends on 11)

The device of claim 11, wherein:
the cache memory includes a set of line type entries that are each configured to store a respective value that specifies whether a respective line of the set of cache lines is configured to store the first type of entry or the second type of entry; and
the cache controller is configured to select the first cache line to evict based on the set of line type entries.

### Claim 13 (depends on 11)

The device of claim 11, wherein:
the device comprises a tag RAM; and
the cache controller is configured to select the first cache line to evict by walking the tag RAM.

### Claim 14 (depends on 11)

The device of claim 11, wherein the cache controller is configured to select the first cache line based on at least one of a first-in-first-out policy, a least recently used policy, or a random replacement policy.

### Claim 15 (depends on 11)

The device of claim 11, wherein:
the cache memory is a victim cache memory; and
the first type of entry is a victim cache entry.

### Claim 16 (depends on 11)

The device of claim 11, wherein the state is an idle state.

### Claim 17

A method comprising:
storing a set of data in a cache line of a cache memory;
storing an indication of whether the set of data is associated with a write-miss entry;
detecting a state of a cache interface; and
based on the state:
selecting the set of data to evict based on the indication; and
evicting the set of data, wherein the evicting includes providing a packet based on the set of data.

### Claim 18 (depends on 17)

The method of claim 17, wherein the selecting of the set of data includes walking a set of tag RAM entries.

### Claim 19 (depends on 17)

The method of claim 17, wherein the selecting of the set of data includes applying at least one of a first-in-first-out policy, a least recently used policy, or a random replacement policy.

### Claim 20 (depends on 17)

The method of claim 17, wherein the indication specifies whether the set of data is associated with the write-miss entry or a victim cache entry.