# US 12,001,344 B2 · Memory access compression using clear code for tile pixels

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- Number: US 12,001,344 B2
- Document ID: US12001344B2
- Status: Granted
- Kind: B2
- Application number: 18/298,142
- Filed: 2023-04-10
- Published: 2023-08-03
- Granted: 2024-06-04
- Earliest claimed: 2017-04-21
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Prasoonkumar Surti; Abhishek R. Appu; Kiran C. Veernapu
- Web page: https://patentgrep.com/patent/US12001344B2

## CPC

- G06F 12/1063: {the data cache being concurrently virtually addressed}
- G06F 12/1009: using page tables, e.g. page table structures
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06T 1/60: Memory management
- G06F 2212/455: Image or video data
- G06F 2212/65: Details of virtual memory and virtual address translation
- G06F 2212/657: Virtual address space management
- G06F 2212/68: Details of translation look-aside buffer [TLB]
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL

## Abstract

One embodiment provides an apparatus comprising a memory device configured to store a page table that includes a set of page table entries and a graphics processing cluster array including a plurality of graphics multiprocessors, the plurality of graphics multiprocessors coupled via a data interconnect. The graphics multiprocessor of the plurality of graphics multiprocessors includes a translation lookaside buffer (TLB) coupled with the memory device, the TLB to cache a first page table entry of the set of page table entries, the first page table entry to indicate that a first virtual page is a valid page that is cleared to a clear color and circuitry to bypass an access to the memory device for the first virtual page and determine a color associated with the first virtual page based on the indication that the first virtual page is a valid page that is cleared to the clear color.

## Claims

### Claim 1

An apparatus comprising:
a memory device configured to store a page table that includes a set of page table entries;
a graphics processing cluster array including a plurality of graphics multiprocessors, the plurality of graphics multiprocessors coupled via a data interconnect, a graphics multiprocessor of the plurality of graphics multiprocessors including:
a translation lookaside buffer (TLB) coupled with the memory device, the TLB to cache a first page table entry of the set of page table entries, the first page table entry to indicate that a first virtual page is a valid page that is cleared to a clear color; and
circuitry to bypass an access to the memory device for the first virtual page and determine a color associated with the first virtual page based on the indication that the first virtual page is a valid page that is cleared to the clear color.

### Claim 2 (depends on 1)

The apparatus as in claim 1, wherein the circuitry is configured to provide a pixel pipeline, a depth pipeline, and an unordered access pipeline, the unordered access pipeline is to generate unordered output to an unordered access view target.

### Claim 3 (depends on 2)

The apparatus as in claim 2, wherein the color associated with the first virtual page is the clear color and the circuitry is to determine the clear color via a register within the graphics multiprocessor.

### Claim 4 (depends on 3)

The apparatus as in claim 3, wherein the circuitry is to read a register index from a TLB entry that caches the first page table entry and the register is associated with the register index.

### Claim 5 (depends on 1)

The apparatus as in claim 1, wherein a second page table entry is to indicate that a second virtual page stores non-clear color data and the circuitry is to perform a memory access to read the non-clear color data from memory associated with the second virtual page.

### Claim 6 (depends on 1)

The apparatus as in claim 1, wherein the color associated with the first virtual page is a clear color that is stored in a dedicated clear color register.

### Claim 7 (depends on 6)

The apparatus as in claim 6, wherein the dedicated clear color register is one of multiple dedicated clear color registers.

### Claim 8 (depends on 7)

The apparatus as in claim 7, wherein the multiple dedicated clear color registers are indexed registers.

### Claim 9 (depends on 1)

The apparatus as in claim 1, wherein the memory device includes a 3D stacked memory.

### Claim 10 (depends on 9)

The apparatus as in claim 9, wherein the 3D stacked memory includes a high bandwidth memory (HBM).

### Claim 11

A method performed by a parallel processor, the method comprising:
accessing a translation lookaside buffer (TLB) entry for a virtual address; and
determining, based on the TLB entry, a clear status for a virtual page associated with the virtual address, wherein the clear status indicates that the virtual page is a valid page that is cleared to a clear color; and
determining the clear color associated with the virtual page by reading the clear color from a register within the parallel processor.

### Claim 12 (depends on 11)

The method as in claim 11, wherein the register within the parallel processor is associated with a register index and further comprising reading the register index from the TLB entry.

### Claim 13 (depends on 12)

The method as in claim 12, wherein the register index selects a register from a set of dedicated clear colors.

### Claim 14 (depends on 11)

The method as in claim 11, wherein the TLB entry is a first TLB entry, the virtual address is a first virtual address for a first virtual page, and the first virtual page is associated with a surface having a first clear color.

### Claim 15 (depends on 14)

The method as in claim 14, additionally comprising;
accessing a second TLB entry for second virtual address; and
determining, based on the second TLB entry, a clear status for a second virtual page associated with the second virtual address, wherein the clear status indicates that the second virtual page is clear and a second clear color is determined via access to a register specified by an index stored within the second TLB entry.

### Claim 16

A data processing system comprising:
a memory device configured to store a page table that includes a set of page table entries;
a plurality of processors including a general-purpose graphics processing unit (GPGPU), the GPGPU including:
a translation lookaside buffer (TLB) to cache a page table entry of the set of page table entries, the page table entry to indicate that a first virtual page is a valid page that is cleared to a clear color; and
circuitry to bypass a memory access for the first virtual page based on the page table entry and determine the clear color for the first virtual page via a read from a register associated with the GPGPU.

### Claim 17 (depends on 16)

The data processing system as in claim 16, wherein the page table entry is to indicate that a second virtual page stores non-clear color data and the circuitry is to perform a memory access to read the non-clear color data from the second virtual page.

### Claim 18 (depends on 16)

The data processing system as in claim 16, wherein the circuitry is associated with one or more of a pixel pipeline, a depth pipeline, or an unordered access pipeline and the memory device includes a 3D stacked memory.

### Claim 19 (depends on 16)

The data processing system as in claim 16, wherein the circuitry is to determine a clear color without performing an access to the memory device for the first virtual page.

### Claim 20 (depends on 16)

The data processing system as in claim 16, wherein the circuitry is to read a register index from a TLB entry that caches the page table entry and the register associated with the circuitry is identified via the register index.