# US 12,001,340 B2 · Full multi-plane operation enablement

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- Number: US 12,001,340 B2
- Document ID: US12001340B2
- Status: Granted
- Kind: B2
- Application number: 18/124,447
- Filed: 2023-03-21
- Published: 2023-09-21
- Granted: 2024-06-04
- Earliest claimed: 2019-12-30
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Jiangang Wu; Qisong Lin; Jung Sheng Hoei; Yunqiu Wan; Ashutosh Malshe; Peng-Cheng Chen
- Web page: https://patentgrep.com/patent/US12001340B2

## CPC

- G06F 11/1666: {where the redundant component is memory or memory area}
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 11/14: Error detection or correction of the data by redundancy in operations (error detection or correction of the data by redundancy in hardware G06F11/16)
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0882: Page mode
- G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}
- G11C 29/00: Checking stores for correct operation {; Subsequent repair}; Testing stores during standby or offline operation
- G06F 13/1668: {Details of memory controller}
- G06F 2212/7209: Validity control, e.g. using flags, time stamps or sequence numbers
- G11C 16/06: Auxiliary circuits, e.g. for writing into memory
- G11C 16/10: Programming or data input circuits
- G11C 16/16: for erasing blocks, e.g. arrays, words, groups
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.

## Claims

### Claim 1

A method comprising:
determining that a quantity of planes of a set of planes of a memory die are invalid planes;
duplicating, based on determining the quantity of the invalid planes, commands of one or more valid planes of the set of planes; and
issuing, based on duplicating the commands of the one or more valid planes, a single descriptor associated with a multi-plane operation for the set of planes of the memory die, wherein the single descriptor comprises a command sequence for the multi-plane operation.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
replacing addresses for each of the quantity of the invalid planes with an address associated with a valid plane in the command sequence for the multi-plane operation indicated by the single descriptor.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
replacing an address of a first plane of the set of planes with an address of a second plane of the set of planes; and
replacing an address of a third plane of the set of planes with an address of a fourth plane of the set of planes, wherein the first plane and the third plane are the invalid planes and the second plane and the fourth plane are valid planes.

### Claim 4 (depends on 1)

The method of claim 1, wherein a first command of the command sequence is a duplicate of a second command of the command sequence, and a third command of the command sequence is a duplicate of a fourth command of the command sequence.

### Claim 5 (depends on 1)

The method of claim 1, wherein determining that the quantity of planes of the set of planes are the invalid planes is based on the quantity of planes containing an amount of invalid data, the quantity of planes exceeding a threshold quantity of invalid pages of the memory die, or both.

### Claim 6 (depends on 1)

The method of claim 1, wherein issuing the single descriptor further comprises:
issuing the single descriptor to a local memory controller of the memory die.

### Claim 7 (depends on 1)

The method of claim 1, wherein the single descriptor comprises commands for valid planes of the set of planes.

### Claim 8 (depends on 1)

The method of claim 1, wherein the command sequence is associated with at least one of a read operation, a write operation, or an erase operation.

### Claim 9

A memory system, comprising:
processing circuitry associated with one or more memory devices, wherein the processing circuitry is configured to cause the memory system to:
determine that a quantity of planes of a set of planes of a memory die are invalid planes;
duplicate, based on determining the quantity of the invalid planes, commands of one or more valid planes of the set of planes; and
issue, based on duplicating the commands of the one or more valid planes, a single descriptor associated with a multi-plane operation for the set of planes of the memory die, wherein the single descriptor comprises a command sequence for the multi-plane operation.

### Claim 10 (depends on 9)

The memory system of claim 9, wherein the processing circuitry is further configured to cause the memory system to:
replace addresses for each of the quantity of the invalid planes with an address associated with a valid plane in the command sequence for the multi-plane operation indicated by the single descriptor.

### Claim 11 (depends on 9)

The memory system of claim 9, wherein the processing circuitry is further configured to cause the memory system to:
replace an address of a first plane of the set of planes with an address of a second plane of the set of planes; and
replace an address of a third plane of the set of planes with an address of a fourth plane of the set of planes, wherein the first plane and the third plane are the invalid planes and the second plane and the fourth plane are valid planes.

### Claim 12 (depends on 9)

The memory system of claim 9, wherein a first command of the command sequence is a duplicate of a second command of the command sequence, and a third command of the command sequence is a duplicate of a fourth command of the command sequence.

### Claim 13 (depends on 9)

The memory system of claim 9, wherein determining that the quantity of planes of the set of planes are the invalid planes is based on the quantity of planes containing an amount of invalid data, the quantity of planes exceeding a threshold quantity of invalid pages of the memory die, or both.

### Claim 14 (depends on 9)

The memory system of claim 9, wherein issuing the single descriptor is further configured to cause the memory system to:
issue the single descriptor to a memory controller of the memory die.

### Claim 15 (depends on 9)

The memory system of claim 9, wherein the single descriptor comprises commands for valid planes of the set of planes.

### Claim 16 (depends on 9)

The memory system of claim 9, wherein the command sequence is associated with at least one of a read operation, a write operation, or an erase operation.

### Claim 17

A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to:
determine that a quantity of planes of a set of planes of a memory die are invalid planes;
duplicate, based on determining the quantity of the invalid planes, commands of one or more valid planes of the set of planes; and
issue, based on duplicating the commands of the one or more valid planes, a single descriptor associated with a multi-plane operation for the set of planes of the memory die, wherein the single descriptor comprises a command sequence for the multi-plane operation.

### Claim 18 (depends on 17)

The non-transitory computer-readable medium of claim 17, wherein the instructions are further executable by the processor to:
replace addresses for each of the quantity of the invalid planes with an address associated with a valid plane in the command sequence for the multi-plane operation indicated by the single descriptor.

### Claim 19 (depends on 17)

The non-transitory computer-readable medium of claim 17, wherein the instructions are further executable by the processor to:
replace an address of a first plane of the set of planes with an address of a second plane of the set of planes; and
replace an address of a third plane of the set of planes with an address of a fourth plane of the set of planes, wherein the first plane and the third plane are the invalid planes and the second plane and the fourth plane are valid planes.

### Claim 20 (depends on 17)

The non-transitory computer-readable medium of claim 17, wherein a first command of the command sequence is a duplicate of a second command of the command sequence, and a third command of the command sequence is a duplicate of a fourth command of the command sequence.