# US 12,001,328 B2 · Controlled input/output in progress state during testcase processing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,001,328 B2 - Document ID: US12001328B2 - Status: Granted - Kind: B2 - Application number: 18/295,865 - Filed: 2023-04-05 - Published: 2023-07-27 - Granted: 2024-06-04 - Earliest claimed: 2021-09-23 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Robert Miller, Jr.; Harris M. Morgenstern; Charles Eugene Mari; Christopher Lee Wood; Alfred Francis Foster - Web page: https://patentgrep.com/patent/US12001328B2 ## CPC - G06F 11/3688: {for test execution, e.g. scheduling of test suites} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/065: {Replication mechanisms} - G06F 3/0664: {at device level, e.g. emulation of a storage device or system} - G06F 3/0683: {Plurality of storage devices} - G06F 11/3636: {by tracing the execution of the program} - G06F 11/3684: {for test design, e.g. generating new test cases} - G06F 11/3696: {Methods or tools to render software testable} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A transient input/output in progress state is established during processing of a testcase by a test infrastructure in a computing environment. The method includes obtaining the testcase for an object having one or more pages, and processing the testcase by the test infrastructure. Processing the testcase by the test infrastructure includes, for a page of the object, generating a delay in the processing of the testcase for the page of the object. The delay opens a transient input/output in progress state during which one or more test operations reference the page of the object. ## Claims ### Claim 1 A computer program product for facilitating processing within a computing environment, the computer program product comprising: at least one computer-readable storage medium having program instructions embodied therewith, the program instructions being readable by a processing circuit to cause the processing circuit to perform a method comprising: obtaining a testcase for an object having one or more pages; and processing the testcase by a test infrastructure, the processing comprising, for a page of the object: generating a delay in the processing of the testcase for the page of the object, the delay opening a transient input/output in progress state during which one or more test operations reference the page of the object. ### Claim 2 (depends on 1) The computer program product of claim 1, further comprising performing the one or more test operations during processing of the testcase, wherein a test operation of the one or more test operations is created by the testcase. ### Claim 3 (depends on 2) The computer program product of claim 2, further comprising testing a system, the testing including the obtaining and the processing, and wherein the method further comprises: detecting an error in the system resulting from performing the one or more test operations; and performing an action based on detecting the error to facilitate correcting the system. ### Claim 4 (depends on 1) The computer program product of claim 1, wherein the obtained testcase specifies a breakpoint routine, and generating the delay is based on the breakpoint routine. ### Claim 5 (depends on 1) The computer program product of claim 1, wherein the testcase includes a page map control structure for the object, the page map control structure specifying a delay parameter, and generating the delay is based on the delay parameter of the page map control structure. ### Claim 6 (depends on 1) The computer program product of claim 1, wherein the testcase comprises an input/output operation, the test infrastructure performing the input/output operation as a virtual memory to virtual memory copy operation, the delay opening the transient input/output in progress state during the virtual memory to virtual memory copy operation. ### Claim 7 (depends on 1) The computer program product of claim 1, further comprising: assigning the object to an object area of virtual memory managed by the test infrastructure; wherein the testcase further establishes a relationship between a window of testcase virtual memory and the object; and wherein processing the testcase by the test infrastructure includes performing a memory-to-memory copy by the test infrastructure in place of an input/output operation to an object storage device, the memory-to-memory copy being between the window of testcase virtual memory and the object area of the virtual memory managed by the test infrastructure. ### Claim 8 (depends on 1) The computer program product of claim 1, wherein generating the delay comprises remaining in the transient input/output in progress state until a predefined event has occurred. ### Claim 9 (depends on 1) The computer program product of claim 1, wherein the testcase is an output testcase, and the test infrastructure comprises an output test infrastructure, and wherein the generated delay is based on a breakpoint intercept routine specified by the testcase or a delay specified in a page map control structure by the testcase. ### Claim 10 (depends on 1) The computer program product of claim 1, wherein the testcase is an input testcase, and the test infrastructure comprises an input test infrastructure, and wherein the generated delay is based on a breakpoint exit routine specified by the testcase or a delay specified in a page map control structure by the testcase. ### Claim 11 A computer system for facilitating processing within a computing environment, the computer system comprising: a memory; and a processing circuit in communication with the memory, wherein the computer system is configured to perform a method, the method comprising: obtaining a testcase for an object having one or more pages; and processing the testcase by a test infrastructure, the processing comprising, for a page of the object: generating a delay in the processing of the testcase for the page of the object, the delay opening a transient input/output in progress state during which one or more test operations reference the page of the object. ### Claim 12 (depends on 11) The computer system of claim 11, further comprising performing one or more test operations during processing of the testcase, wherein a test operation of the one or more test operations is created by the testcase. ### Claim 13 (depends on 11) The computer system of claim 11, wherein the obtained testcase specifies a breakpoint routine, and generating the delay is based on the breakpoint routine. ### Claim 14 (depends on 11) The computer system of claim 11, wherein the testcase includes a page map control structure for the object, the page map control structure specifying a delay parameter, and generating the delay is based on the delay parameter of the page map control structure. ### Claim 15 (depends on 11) The computer system of claim 11, wherein the testcase comprises an input/output operation, the test infrastructure performing the input/output operation as a virtual memory to virtual memory copy operation, the delay opening the transient input/output in progress state during the virtual memory to virtual memory copy operation. ### Claim 16 (depends on 11) The computer system of claim 11, further comprising: assigning the object to an object area of virtual memory managed by the test infrastructure; wherein the testcase further establishes a relationship between a window of testcase virtual memory and the object; and wherein processing the testcase by the test infrastructure includes performing a memory-to-memory copy by the test infrastructure in place of an input/output operation to an object storage device, the memory-to-memory copy being between the window of testcase virtual memory and the object area of the virtual memory managed by the test infrastructure. ### Claim 17 A computer-implemented method comprising: obtaining a testcase for an object having one or more pages, the testcase including a page map control structure for the object, the page map control structure specifying one or more delay parameters; and processing the testcase by a test infrastructure, the processing comprising, for a page of the object: generating a delay in the processing of the testcase for the page of the object, the delay opening a transient input/output in progress state during which one or more test operations reference the page of the object. ### Claim 18 (depends on 17) The computer-implemented method of claim 17, further comprising performing one or more test operations during processing of the testcase. ### Claim 19 (depends on 17) The computer-implemented method of claim 17, wherein the obtained testcase specifies a breakpoint routine, and generating the delay is based on the breakpoint routine. ### Claim 20 (depends on 17) The computer-implemented method of claim 17, wherein the testcase includes a page map control structure for the object, the page map control structure specifying a delay parameter, and generating the delay is based on the delay parameter of the page map control structure.