# US 12,001,288 B2 · Devices and methods for safe mode of operation in event of memory channel misbehavior

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- Number: US 12,001,288 B2
- Document ID: US12001288B2
- Status: Granted
- Kind: B2
- Application number: 17/484,310
- Filed: 2021-09-24
- Published: 2023-03-30
- Granted: 2024-06-04
- Earliest claimed: 2021-09-24
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Kunal Desai; Kiran Kumar Malipeddi; Shekar Babu Merla; Pranav Agrawal
- Web page: https://patentgrep.com/patent/US12001288B2

## CPC

- G06F 11/0724: {in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80)}
- G06F 11/1428: {with loss of hardware functionality}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 11/1417: {Boot up procedures}
- G06F 11/142: {Reconfiguring to eliminate the error (group management mechanisms in a peer-to-peer network H04L67/1044)}
- G06F 11/2033: {switching over of hardware resources}
- G06F 11/2284: {by power-on test, e.g. power-on self test [POST]}
- G06F 13/1668: {Details of memory controller}
- G11C 29/38: Response verification devices
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Various embodiments may include methods and systems for reconfiguring memory channel routing within a system-on-a-chip (SoC). A method may include obtaining first error information in response to misbehavior in a first memory channel communicatively connected to a network interface unit (NIU) of the SoC. The method may further include storing the first error information in non-volatile memory that is read upon booting of the SoC, and rebooting the SoC including the first memory channel. The method may further include configuring the first memory channel to be communicatively disconnected from the NIU and configuring a second memory channel to be communicatively connected to the NIU in response to reading the stored first error information during reboot.

## Claims

### Claim 1

A method for reconfiguring memory channel routing within a system-on-a-chip (SoC), comprising:
obtaining first error information in response to misbehavior in a first memory channel communicatively connected to a network interface unit (NIU) of the SoC;
storing the first error information in non-volatile memory that is read upon booting of the SoC;
rebooting the SoC including the first memory channel;
performing a built-in self-test on the first memory channel during the reboot;
generating second error information and writing the second error information over the first error information in the non-volatile memory in response to the built-in-self-test indicating no misbehavior in the first memory channel during the reboot;
configuring the first memory channel to be communicatively disconnected from the NIU and configuring a second memory channel to be communicatively connected to the NIU in response to reading the first error information in the non-volatile memory during the reboot; and
rebooting the SoC including the first memory channel and the second memory channel in response to no misbehavior in the first memory channel.

### Claim 2 (depends on 1)

The method of claim 1, wherein configuring the first memory channel to be communicatively disconnected from the NIU and configuring the second memory channel to be communicatively connected to the NIU in response to reading the stored first error information during reboot comprises:
reprogramming control/status registers (CSRs) to adjust address mapping of the NIU to disconnect the NIU from the first memory channel and to connect the NIU to the second memory channel.

### Claim 3 (depends on 1)

The method of claim 1, wherein configuring the first memory channel to be communicatively disconnected from the NIU and configuring the second memory channel to be communicatively connected to the NIU in response to reading the stored first error information during reboot comprises:
reprogramming control/status registers (CSRs) to configure a multiplexor to disconnect the NIU from the first memory channel and to connect the NIU to the second memory channel.

### Claim 4 (depends on 1)

The method of claim 1, further comprising detecting misbehavior in the first memory channel based on at least one of error correction codes, parity bits corresponding to address mapping and control registers, or a timeout-per-transaction function.

### Claim 5 (depends on 1)

The method of claim 1, further comprising detecting misbehavior in the first memory channel based on at least one of error correction codes to or from dynamic random-access memory (DRAM) of the first memory channel, error correction codes for LLCC cache, or error correction codes for LLCC tags.

### Claim 6 (depends on 1)

The method of claim 1, wherein configuring the first memory channel to be communicatively disconnected from the NIU and configuring the second memory channel to be communicatively connected to the NIU in response to reading the stored first error information during reboot comprises:
in response to the stored first error information indicating misbehavior in a first physical interface (PHY) of the first memory channel:
configuring the first memory channel to be communicatively disconnected from the NIU and configuring the second memory channel to be communicatively connected to the NIU; and
configuring a second PHY of the second memory channel to be communicatively connected to dynamic random-access memory (DRAM) of the first memory channel.

### Claim 7 (depends on 1)

The method of claim 1, wherein configuring the first memory channel to be communicatively disconnected from the NIU and configuring the second memory channel to be communicatively connected to the NIU in response to reading the stored first error information during reboot comprises:
in response to the stored first error information indicating misbehavior in a first memory controller of the first memory channel:
configuring the first memory channel to be communicatively disconnected from the NIU and configuring the second memory channel to be communicatively connected to the NIU; and
configuring a second memory controller of the second memory channel to be communicatively connected a physical interface (PHY) of the first memory channel.

### Claim 8

A system-on-a-chip (SoC), comprising:
a network interface unit (NIU);
a first memory channel capable of being communicatively connected to the NIU;
a second memory channel capable of being communicatively connected to the NIU; and
a non-volatile memory configured to store first error information that is read upon booting of the SoC;
wherein the SoC is configured to:
obtain the first error information in response to misbehavior in the first memory channel when communicatively connected to the NIU;
store the first error information in the non-volatile memory;
reboot the SoC including the first memory channel;
perform a built-in self-test on the first memory channel during the reboot;
generate second error information and write the second error information over the first error information in the non-volatile memory in response to the built-in-self-test indicating no misbehavior in the first memory channel during the reboot;
configure the first memory channel to be communicatively disconnected from the NIU and configure the second memory channel to be communicatively connected to the NIU in response to reading the first error information in the non-volatile memory during the reboot; and
reboot the SoC including the first memory channel and the second memory channel in response to no misbehavior in the first memory channel.

### Claim 9 (depends on 8)

The SoC of claim 8, wherein the SoC is further configured to configure the first memory channel to be communicatively disconnected from the NIU and configure the second memory channel to be communicatively connected to the NIU in response to reading the stored first error information during reboot by:
reprogramming control/status registers (CSRs) to adjust address mapping of the NIU to disconnect the NIU from the first memory channel and to connect the NIU to the second memory channel.

### Claim 10 (depends on 8)

The SoC of claim 8, wherein the SoC is further configured to configure the first memory channel to be communicatively disconnected from the NIU and configure the second memory channel to be communicatively connected to the NIU in response to reading the stored first error information during reboot by:
reprogramming control/status registers (CSRs) to configure a multiplexor to disconnect the NIU from the first memory channel and to connect the NIU to the second memory channel.

### Claim 11 (depends on 8)

The SoC of claim 8, wherein the SoC is further configured to detect misbehavior in the first memory channel based on at least one of error correction codes, parity bits corresponding to address mapping and control registers, or a timeout-per-transaction function.

### Claim 12 (depends on 8)

The SoC of claim 8, wherein the SoC is further configured to detect misbehavior in the first memory channel based on at least one of error correction codes to or from dynamic random-access memory (DRAM) of the first memory channel, error correction codes for LLCC cache, or error correction codes for LLCC tags.

### Claim 13 (depends on 8)

The SoC of claim 8, wherein the SoC is further configured to configure the first memory channel to be communicatively disconnected from the NIU and configure the second memory channel to be communicatively connected to the NIU in response to reading the stored first error information during reboot by in response to the stored first error information indicating misbehavior in a first physical interface (PHY) of the first memory channel:
configuring the first memory channel to be communicatively disconnected from the NIU and configuring the second memory channel to be communicatively connected to the NIU; and
configuring a second PHY of the second memory channel to be communicatively connected to dynamic random-access memory (DRAM) of the first memory channel.

### Claim 14 (depends on 8)

The SoC of claim 8, wherein the SoC is further configured to configure the first memory channel to be communicatively disconnected from the NIU and configure the second memory channel to be communicatively connected to the NIU in response to reading the stored first error information during reboot in response to the stored first error information indicating misbehavior in a first memory controller of the first memory channel by:
configuring the first memory channel to be communicatively disconnected from the NIU and the second memory channel to be communicatively connected to the NIU; and
configuring a second memory controller of the second memory channel to be communicatively connected a physical interface (PHY) of the of the first memory channel.

### Claim 15 (depends on 8)

The SoC of claim 8, wherein the first memory channel and the second memory channel are double data rate (DDR) channels.

### Claim 16

A non-transitory processor-readable medium having stored thereon processor-executable instructions configured to cause a processor to reconfigure memory channel routing within a system-on-a-chip (SoC) to perform operations comprising:
obtaining first error information in response to misbehavior in a first memory channel communicatively connected to a network interface unit (NIU) of the SoC;
storing the first error information in non-volatile memory that is read upon booting of the SoC;
rebooting the SoC including the first memory channel;
performing a built-in self-test on the first memory channel during the reboot;
generating second error information and writing the second error information over the first error information in the non-volatile memory in response to the built-in-self-test indicating no misbehavior in the first memory channel during the reboot;
configuring the first memory channel to be communicatively disconnected from the NIU and configuring a second memory channel to be communicatively connected to the NIU in response to reading the first error information in the non-volatile memory during the reboot; and
rebooting the SoC including the first memory channel and the second memory channel in response to no misbehavior in the first memory channel.