# US 12,001,282 B2 · Write control for read-modify-write operations in cache memory

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- Number: US 12,001,282 B2
- Document ID: US12001282B2
- Status: Granted
- Kind: B2
- Application number: 17/956,136
- Filed: 2022-09-29
- Published: 2023-01-19
- Granted: 2024-06-04
- Earliest claimed: 2019-05-24
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Abhijeet Ashok Chachad; Timothy David Anderson; David Matthew Thompson; Daniel Brad Wu
- Web page: https://patentgrep.com/patent/US12001282B2

## CPC

- G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/064: {Management of blocks}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F 3/0685: {Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays}
- G06F 9/3816: {Instruction alignment, e.g. cache line crossing}
- G06F 11/1064: {in cache or content addressable memories}
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0815: Cache consistency protocols
- G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
- G06F 12/126: with special data handling, e.g. priority of data or instructions, handling errors or pinning
- H04W 24/10: Scheduling measurement reports {; Arrangements for measurement reports}
- H04W 56/001: {Synchronization between nodes}
- H04W 72/02: Selection of wireless resources by user or terminal
- H04W 72/044: based on the type of the allocated resource
- H04W 74/0841: {with collision treatment}
- H04W 74/0866: {using a dedicated channel for access}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G06F 2212/1024: Latency reduction
- G06F 2212/608: Details relating to cache mapping
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72)

## Abstract

In described examples, a processor system includes a processor core that generates memory write requests, and a cache memory with a memory controller having a memory pipeline. The cache memory has cache lines of length L. The cache memory has a minimum write length that is less than a cache line length of the cache memory. The memory pipeline determines whether the data payload includes a first chunk and ECC syndrome that correspond to a partial write and are writable by a first cache write operation, and a second chunk and ECC syndrome that correspond to a full write operation that can be performed separately from the first cache write operation. The memory pipeline performs an RMW operation to store the first chunk and ECC syndrome in the cache memory, and performs the full write operation to store the second chunk and ECC syndrome in the cache memory.

## Claims

### Claim 1

A system comprising:
at least one processor;
a cache memory including a minimum write length (M) and a memory line length (L), wherein L/M is a first integer; and
a memory controller coupled to the at least one processor and the cache memory, the memory controller configured to perform a read modify write (RMVV) operation in response to a memory write request including a data payload, wherein:
the memory controller performs the RMW operation on a set of conforming chunks of conforming data from the cache memory based on the first integer; and
the RMW operation is configured to:
retrieve the conforming data from the cache memory that corresponds to the set of conforming chunks;
merge the conforming data with the data payload, wherein the merge overwrites a portion of the conforming data to produce merged data; and
store the merged data in the cache memory.

### Claim 2 (depends on 1)

The system of claim 1, wherein the memory controller is configured to:
perform the RMW operation in response to a flag indicating a partial write.

### Claim 3 (depends on 1)

The system of claim 1, wherein:
the conforming data is retrieved from the cache memory corresponding to an address of the data payload.

### Claim 4 (depends on 1)

The system of claim 1, wherein:
the set of conforming chunks correspond to a cache line length and a set of conforming ECC syndromes.

### Claim 5 (depends on 4)

The system of claim 4, wherein the memory controller is configured to:
update the set of conforming ECC syndromes to form updated corresponding ECC syndromes; and
store the updated corresponding ECC syndromes in the cache memory.

### Claim 6 (depends on 1)

The system of claim 1, wherein:
each of the set of conforming chunks includes a chunk length (P); and
M/P is a second integer.

### Claim 7 (depends on 6)

The system of claim 6, wherein:
L/P is a third integer.

### Claim 8 (depends on 7)

The system of claim 7, wherein:
in response to the first integer and the third integer being equal to or greater than 1, the set of conforming chunks is based on the second integer.

### Claim 9 (depends on 1)

The system of claim 1, wherein:
in response to the first integer being greater than or equal to 2, the set of conforming chucks is less than all chunks of the conforming data.

### Claim 10 (depends on 1)

The system of claim 1, wherein the memory controller is configured to:
detect an error in the set of conforming chunks; and
correct the error.

### Claim 11

A method comprising:
receiving, by a memory controller, a memory write request including a data payload;
in response to the memory write request indicating a read modify write (RMW) operation, performing the RMW operation on a set of conforming chunks of conforming data from a cache memory, the set of conforming chunks based on a first integer corresponding to a ratio of a minimum write length (M) of a cache memory and a memory line length (L) of the cache memory, wherein the RMW operation includes:
retrieving the conforming data from the cache memory that corresponds to the set of conforming chunks;
merging the conforming data with the data payload, wherein the merge overwrites a portion of the conforming data to produce merged data; and
storing the merged data in the cache memory.

### Claim 12 (depends on 11)

The method of claim 11, wherein:
the memory write request includes a flag indicating a partial write.

### Claim 13 (depends on 11)

The method of claim 11, wherein:
the conforming data is retrieved from the cache memory corresponding to an address of the data payload.

### Claim 14 (depends on 11)

The method of claim 11, wherein:
the set of conforming chunks correspond to a cache line length and a set of conforming ECC syndromes.

### Claim 15 (depends on 14)

The method of claim 14, wherein the memory controller is configured to:
update the set of conforming ECC syndromes to form updated corresponding ECC syndromes; and
store the updated corresponding ECC syndromes in the cache memory.

### Claim 16 (depends on 11)

The method of claim 11, wherein:
each of the set of conforming chunks includes a chunk length (P); and
M/P is a second integer.

### Claim 17 (depends on 16)

The method of claim 16, wherein:
UP is a third integer.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
in response to the first integer and the third integer being equal to or greater than 1, the set of conforming chunks is based on the second integer.

### Claim 19 (depends on 11)

The method of claim 11, wherein:
in response to the first integer being greater than or equal to 2, the set of conforming chucks is less than all chunks of the conforming data.

### Claim 20 (depends on 11)

The method of claim 11, wherein the RMW operation includes:
detecting an error in the set of conforming chunks; and
correcting the error.