# US 12,001,281 B2 · Deferred error code correction with improved effective data bandwidth performance

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- Number: US 12,001,281 B2
- Document ID: US12001281B2
- Status: Granted
- Kind: B2
- Application number: 17/192,030
- Filed: 2021-03-04
- Published: 2021-06-24
- Granted: 2024-06-04
- Earliest claimed: 2019-03-14
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Gil Golov
- Web page: https://patentgrep.com/patent/US12001281B2

## CPC

- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 11/1052: {Bypassing or disabling error detection or correction}
- G06F 12/0804: with main memory updating (G06F12/0806 takes precedence)
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G06F 3/0656: {Data buffering arrangements}
- G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)}
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- G06F 2212/403: Error protection encoding, e.g. using parity or ECC codes
- G06F 2212/608: Details relating to cache mapping
- G11C 11/40607: {Refresh operations in memory devices with an internal cache or data buffer}
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 2029/0411: {Online error correction}
- G11C 2207/2245: Memory devices with an internal cache buffer
- G11C 2211/4062: Parity or ECC in refresh operations
- H03M 13/098: {using single parity bit}
- H03M 13/11: using multiple parity bits
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A deferred error correction code (ECC) scheme for memory devices is disclosed. In one embodiment, a method is disclosed comprising starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition; receiving an operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; deferring ECC operations for the operation; executing the operation; detecting an end of the deferred period of operation; and executing the ECC operations after the end of the deferred period.

## Claims

### Claim 1

A method comprising:
starting a deferred period of operation of a memory system in response to detecting a satisfaction of a condition, wherein, during the deferred period of operation, an error code correction (ECC) portion of a memory bank is not accessed during operations;
issuing a command to read data from or write data to the memory bank of the memory system in response to an operation received from a processor during the deferred period of operation;
generating ECC data prior to receiving a response to the command from the memory bank during the deferred period of operation;
caching the ECC data in a local cache; and
returning a result of the command to the processor while the ECC data is present in the local cache.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
receiving the operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; and
executing the operation prior to issuing the command to the memory bank of the memory system.

### Claim 3 (depends on 1)

The method of claim 1, the detecting the satisfaction of the condition comprising detecting one of:
a receipt of a second command to start the deferred period from the processor; or
a data bus utilization above a predetermined threshold.

### Claim 4 (depends on 2)

The method of claim 2, the operation comprising a write operation and the generating ECC data comprising:
generating ECC parity bits based on data in the write operation; and
storing the ECC parity bits and an address associated with the data in the local cache.

### Claim 5 (depends on 4)

The method of claim 4, further comprising writing the ECC parity bits to the memory bank using the address.

### Claim 6 (depends on 2)

The method of claim 2, the operation comprising a read operation and the generating ECC data comprising generating an ECC syndrome based on data in the read operation; and storing the ECC syndrome and an address associated with the data in the local cache.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
detecting a mismatch using the ECC syndrome; and
in response to detecting the mismatch, alerting the processor that an error executing the read operation occurred.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
detecting an end of the deferred period of operation; and
executing ECC operations after the end of the deferred period.

### Claim 9 (depends on 8)

The method of claim 8, the detecting the end of the deferred period comprising detecting one of: a receipt of a third command to stop the deferred period from the processor; a data bus utilization below a predetermined threshold; or the local cache is full.

### Claim 10

A non-transitory computer-readable storage medium for tangibly storing computer program instructions capable of being executed by a computer processor, the computer program instructions defining steps of:
starting a deferred period of operation of a memory system in response to detecting a satisfaction of a condition, wherein, during the deferred period of operation, an error code correction (ECC) portion of a memory bank is not accessed during operations;
issuing a command to read data from or write data to the memory bank of the memory system in response to an operation received from a processor during the deferred period of operation;
generating ECC data prior to receiving a response to the command from the memory bank during the deferred period of operation;
caching the ECC data in a local cache; and
returning a result of the command to the processor while the ECC data is present in the local cache.

### Claim 11 (depends on 10)

The non-transitory computer-readable storage medium of claim 10, the computer program instructions further defining steps of:
receiving the operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; and
executing the operation prior to issuing the command to the memory bank of the memory system.

### Claim 12 (depends on 10)

The non-transitory computer-readable storage medium of claim 10, the detecting the satisfaction of the condition comprising detecting one of:
a receipt of a second command to start the deferred period from the processor; or
a data bus utilization above a predetermined threshold.

### Claim 13 (depends on 10)

The non-transitory computer-readable storage medium of claim 10, the operation comprising a write operation and the generating ECC data comprising:
generating ECC parity bits based on data in the write operation; and
storing the ECC parity bits and an address associated with the data in the local cache.

### Claim 14 (depends on 10)

The non-transitory computer-readable storage medium of claim 10, the operation comprising a read operation and the generating ECC data comprising generating an ECC syndrome based on data in the read operation; and storing the ECC syndrome and an address associated with the data in the local cache.

### Claim 15

A memory system comprising:
a plurality of memory banks;
a bus connected to the memory banks; and
a controller connected to the bus, the controller configured to perform operations of:
starting a deferred period of operation of a memory system in response to detecting a satisfaction of a condition, wherein, during the deferred period of operation, an error code correction (ECC) portion of a memory bank is not accessed during operations;
issuing a command to read data from or write data to the memory bank of the memory system in response to an operation received from a processor during the deferred period of operation;
generating ECC data prior to receiving a response to the command from the memory bank during the deferred period of operation;
caching the ECC data in a local cache; and
returning a result of the command to the processor while the ECC data is present in the local cache.

### Claim 16 (depends on 15)

The memory system of claim 15, the operations further comprising:
receiving the operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; and
executing the operation prior to issuing the command to the memory bank of the memory system.

### Claim 17 (depends on 15)

The memory system of claim 15, the detecting the satisfaction of the condition comprising detecting one of:
a receipt of a second command to start the deferred period from the processor; or
a data bus utilization above a predetermined threshold.

### Claim 18 (depends on 15)

The memory system of claim 15, the operation comprising a write operation and the generating ECC data comprising:
generating ECC parity bits based on data in the write operation; and
storing the ECC parity bits and an address associated with the data in the local cache.

### Claim 19 (depends on 18)

The memory system of claim 18, further comprising writing the ECC parity bits to the memory bank using the address.

### Claim 20 (depends on 15)

The memory system of claim 15, the operation comprising a read operation and the generating ECC data comprising generating an ECC syndrome based on data in the read operation; and storing the ECC syndrome and an address associated with the data in the local cache.