# US 12,001,280 B2 · Overcoming error correction coding mis-corrects in non-volatile memory

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- Number: US 12,001,280 B2
- Document ID: US12001280B2
- Status: Granted
- Kind: B2
- Application number: 17/133,995
- Filed: 2020-12-24
- Published: 2021-04-22
- Granted: 2024-06-04
- Earliest claimed: 2020-12-24
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Krishna K. Parat; Ravi H. Motwani; Rohit S. Shenoy; Ali Khakifirooz
- Web page: https://patentgrep.com/patent/US12001280B2

## CPC

- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G06F 11/1072: {in multilevel memories}
- G11C 11/5621: {using charge storage in a floating gate}
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 2211/5644: Multilevel memory comprising counting devices
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Error correction coding (ECC) mis-corrected reads, if undetected, result in silent data corruption of a non-volatile memory device. Overcoming ECC mis-corrected reads is based on a read signature of a result of reading a page in the non-volatile memory device. An ECC mis-correct logic counts the number of bits in the end-most buckets into which the bits of the result is divided. End-most buckets that are overpopulated or starved reveal a tell-tale read signature of an ECC mis-correct. The ECC mis-correct is likely to occur when the read reference voltage level used to read the page is shifted in one direction or another to an extreme amount that risks reading data from a different page. Detecting ECC mis-corrected reads can be used to overcome the ECC mis-corrects and mitigate silent data corruption.

## Claims

### Claim 1

A memory controller comprising:
a read logic to apply a read voltage shift to a read reference voltage level in advance of a read of a page of non-volatile memory cells encoded to store multiple pages;
an error correction coding (ECC) logic to verify that the read of the page was correct;
a mis-correct logic to detect silent data corruption in a non-volatile memory device in which the page is located, including to determine whether the read of the page verified as correct is instead an ECC mis-correct; and
wherein the ECC mis-correct is determined based on a read signature of a result of the read that indicates the result includes data from a different page.

### Claim 2 (depends on 1)

The memory controller of claim 1, further comprising:
a moving read reference (MRR) table of entries containing one or more read voltage shifts to apply to the read reference voltage level in any of a left and right direction;
a threshold voltage shift for checking for a possible mis-correct, the threshold voltage shift representing an extreme shift that risks causing the read logic to read a different page; and
wherein the mis-correct logic is performed upon a determination that the read voltage shift applied to the read reference voltage level any of meets or exceeds the threshold voltage shift.

### Claim 3 (depends on 1)

The memory controller of claim 1, wherein the mis-correct logic includes logic to:
divide bits comprising the result of the read into bit buckets;
count a number of the bits in an end-most bucket of the bit buckets; and
determine the read signature of the result of the read based on the number of the bits counted in the end-most bucket, including any of an overpopulation of bits and a starvation of bits in the end-most bucket.

### Claim 4 (depends on 3)

The memory controller of claim 3, wherein the end-most bucket is any of a left-most bucket and a right-most bucket.

### Claim 5 (depends on 1)

The memory controller of claim 1, wherein the ECC logic to verify that the read of the page was correct is based on an ECC check that is closed under linearity, including a linear ECC codeword applied to the result of the read.

### Claim 6 (depends on 1)

The memory controller of claim 1, wherein the non-volatile memory device is a multi-level NAND, and the page is any one of an upper, lower, extra and top page of the multi-level NAND.

### Claim 7 (depends on 1)

The memory controller of claim 1, wherein a cell of the non-volatile memory cells is encoded to store multiple bits using an encoding scheme, the encoding scheme including any of a Multi-Level Cell (“MLC”), Quad-Level Cell (“QLC”), Tri-Level Cell (“TLC”), Penta-Level Cell (“PLC”) encoding schemes.

### Claim 8

A computer-implemented method comprising:
applying a read voltage shift to a read reference voltage level in advance of a read of a page of non-volatile memory cells encoded to store multiple pages;
verifying that the read of the page was correct in accordance with an error correction coding (ECC) logic;
detecting silent data corruption in a non-volatile memory device containing the non-volatile memory cells in which the page is encoded, including determining whether the read of the page verified as correct is instead an ECC mis-correct; and
wherein the ECC mis-correct is determined based on a read signature of a result of the read that indicates the result includes data from a different page.

### Claim 9 (depends on 8)

The computer-implemented method of claim 8, further comprising:
applying a read voltage shift to the read reference voltage level in any of a left and right direction, the read voltage shift selected from a moving read reference (MRR) table of entries containing one or more read voltage shifts;
receiving a threshold voltage shift for checking for a possible mis-correct, the threshold voltage shift representing an extreme shift that risks reading a different page; and
determining whether the read voltage shift applied to the read reference voltage level any of meets or exceeds the threshold voltage shift.

### Claim 10 (depends on 8)

The computer-implemented method of claim 8, wherein determining whether the read of the page verified as correct is instead the ECC mis-correct includes:
dividing bits comprising the result of the read into bit buckets;
counting a number of the bits in an end-most bucket of the bit buckets; and
determining the read signature of the result of the read based on the number of the bits counted in the end-most bucket, including any of an overpopulation of bits and a starvation of bits in the end-most bucket.

### Claim 11 (depends on 10)

The computer-implemented method of claim 10, wherein the end-most bucket is any of a left-most bucket and a right-most bucket.

### Claim 12 (depends on 8)

The computer-implemented method of claim 8, wherein verifying that the read of the page was correct is based on a linear ECC codeword applied to the result of the read.

### Claim 13 (depends on 8)

The computer-implemented method of claim 8, wherein the non-volatile memory device is a multi-level NAND, and the page is any one of an upper, lower, extra and top page of the multi-level NAND.

### Claim 14 (depends on 8)

The computer-implemented method of claim 8, wherein a cell of the non-volatile memory cells is encoded to store multiple bits using an encoding scheme, the encoding scheme including any of a Multi-Level Cell (“MLC”), Quad-Level Cell (“QLC”), Tri-Level Cell (“TLC”), Penta-Level Cell (“PLC”) encoding schemes.

### Claim 15

A storage system comprising:
an array of non-volatile memory cells encoded to store multiple pages at different read reference voltage levels; and
a memory controller communicatively coupled to the array of non-volatile memory cells, the memory controller having a processor to:
apply a read voltage shift to a read reference voltage level in advance of a read of a page of non-volatile memory cells,
verify that the read of the page was correct in accordance with an error correction coding (ECC) scheme,
determine an ECC mis-correct based on a read signature of a result of the read that indicates the result includes data from a different page, and
detect silent data corruption in a non-volatile memory device containing the array of non-volatile memory cells in which the page is encoded after a determination that the read of the page verified as correct is instead the ECC mis-correct.

### Claim 16 (depends on 15)

The storage system of claim 15, wherein:
the memory controller includes:
a moving read reference (MRR) table of entries containing one or more read voltage shifts to apply to the read reference voltage level in any of a left and right direction;
a threshold voltage shift for checking for a possible mis-correct, the threshold voltage shift representing an extreme shift that risks causing the memory controller to read a different page; and
the processor is further to determine that the read voltage shift applied to the read reference voltage level any of meets or exceeds the threshold voltage shift.

### Claim 17 (depends on 15)

The storage system of claim 15, wherein the processor is further to:
divide bits comprising the result of the read into bit buckets;
count a number of the bits in an end-most bucket of the bit buckets; and
determine the read signature of the result of the read based on the number of the bits counted in the end-most bucket, including any of an overpopulation of bits and a starvation of bits in the end-most bucket.

### Claim 18 (depends on 17)

The storage system of claim 17, wherein the end-most bucket is any of a left-most bucket and a right-most bucket.

### Claim 19 (depends on 15)

The storage system of claim 15, wherein to verify that the read of the page was correct is based on an ECC check that is closed under linearity, including a linear ECC codeword applied to the result of the read.

### Claim 20 (depends on 15)

The storage system of claim 15, wherein the non-volatile memory device containing the array of non-volatile memory cells in which the page is encoded is a multi-level NAND, and the page is any one of an upper, lower, extra and top page of the multi-level NAND.

### Claim 21 (depends on 15)

The storage system of claim 15, wherein a cell of the non-volatile memory cells is encoded to store multiple bits using an encoding scheme, the encoding scheme including any of a Multi-Level Cell (“MLC”), Quad-Level Cell (“QLC”), Tri-Level Cell (“TLC”), Penta-Level Cell (“PLC”) encoding schemes.