# US 12,001,266 B1 · Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,001,266 B1
- Document ID: US12001266B1
- Status: Granted
- Kind: B1
- Application number: 17/408,323
- Filed: 2021-08-20
- Granted: 2024-06-04
- Earliest claimed: 2021-08-06
- Assignees: Kepler Computing Inc.
- Applicants: Kepler Computing Inc.
- Inventors: Amrita Mathuriya; Christopher B. Wilkerson; Rajeev Kumar Dokania; Debo Olaosebikan; Sasikanth Manipatruni
- Web page: https://patentgrep.com/patent/US12001266B1

## CPC

- H10W 40/10: Arrangements for heating
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- G06F 1/206: {comprising thermal management}
- G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode
- G06F 1/3287: by switching off individual functional units in the computer system
- G06F 1/329: by task scheduling
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals}
- G06F 9/54: Interprogram communication
- G06F 15/7821: {Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory}
- G06F 15/7825: {Globally asynchronous, locally synchronous, e.g. network on chip}
- G06F 15/7842: {on one IC chip (single chip microcontrollers)}
- G06F 30/3308: using simulation
- G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- H02M 3/10: using discharge tubes with control electrode or semiconductor devices with control electrode (H02M3/07 takes precedence)
- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 51/40: characterised by the peripheral circuit region
- H10B 53/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 53/40: characterised by the peripheral circuit region
- H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- G06F 2115/10: Processors
- G06F 2117/08: HW-SW co-design, e.g. HW-SW partitioning
- G06F 2119/02: Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
- G06F 2119/06: Power analysis or power optimisation
- G06F 2119/08: Thermal analysis or thermal optimisation
- G06N 20/00: Machine learning
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- H10B: ELECTRONIC MEMORY DEVICES
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

## Claims

### Claim 1

An apparatus comprising:
a first logic block including a first circuitry having ferroelectric logic or paraelectric logic;
a second logic block including a second circuitry having CMOS based logic; and
a power management unit having a third circuitry which is coupled to the first circuitry and the second circuitry, wherein the third circuitry is to manage power of the first logic block and the second logic block,
wherein the power management unit is to compute a first throughput ratio of the first logic block, and wherein the power management unit is to compute a second throughput ratio of the second logic block,
wherein the ferroelectric logic or the paraelectric logic includes at least three capacitors with first terminals to receive inputs and second terminals that are directly coupled to a node, wherein at least one capacitor of the at least three capacitors includes non-linear polar material, wherein the ferroelectric logic or the paraelectric logic includes a reset mechanism coupled to the node, wherein the reset mechanism is operable to reset charge on the node in a reset phase separate from an evaluation phase of the inputs, wherein the first logic block and the second logic block have an overlapping functionality, and wherein the power management unit is operable to manage power of the overlapping functionality in the first logic block and the second logic block.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the overlapping functionality is associated with a math unit.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the first logic block and the second logic block are on separate dies.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the separate dies are configured in a 2.5D or 3D package configuration.

### Claim 5 (depends on 3)

The apparatus of claim 3, wherein the first logic block is part of a first die, wherein the second logic block is part of a second die, wherein the first die is on a substrate, wherein the first die comprises a first compute logic, wherein the second die is stacked on the first die.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the first die and the second die are coupled via micro-bumps, or wherein the first die and the second die are coupled via copper-to-copper bonding.

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein active devices of the first die are closer to active devices of the second die than to the substrate.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the power management unit is to throttle the second logic block and to allocate additional power budget to the first logic block based on the first throughput ratio being greater than the second throughput ratio.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the power management unit is to throttle the first logic block and to allocate additional power to the second logic block based on the second throughput ratio being greater than a scaled version of the first throughput ratio.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the ferroelectric logic or the paraelectric logic include a majority gate, a minority gate, or a threshold gate.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein the non-linear polar material includes one of: a ferroelectric material, a paraelectric material, or a non-linear dielectric.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein the non-linear polar material includes one of:
bismuth ferrite (BFO), or BFO with a first doping material, wherein the first doping material is one of lanthanum or elements from lanthanide series of periodic table;
lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb;
a relaxor ferroelectric which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-Bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a perovskite which includes one of: BaTiO3, PbTiO3, KNbO3, or NaTaO3;
a first hexagonal ferroelectric which includes one of: MnO3 or LuFeO3;
a second hexagonal ferroelectric of a type h-RMnO3, where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y);
hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or their alloyed oxides;
hafnium oxides;
a compound including Al, Sc, and N, a compound including Ga, Sc, and N, a compound including Al, Y, and N, or a compound including Al, Mg, Nb, N, Hf, and O;
niobate type compounds LiNbO3, LiTaO3, lithium iron tantalum oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate; or
an improper ferroelectric which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 and 100, where PTO is compound comprising Pb, Ti, and O, where STO is a compound comprising Sr, Ti, and O, where LAO is a compound comprising La, Al, and O, where PTO/STO is bi-layer of PTO and STO, and where LAO/STO is a bi-layer of LAO and STO.

### Claim 13 (depends on 11)

The apparatus of claim 11, wherein the paraelectric material includes: SrTiO3, a compound of Ba, Sr, Ti, and O, HfZrO2, Hf—Si—O, La-substituted PbTiO3, or lead magnesium niobate-lead titanate (PMN-PT) based relaxor ferroelectrics.

### Claim 14

A system comprising:
a memory;
a first die having a ferroelectric logic or a paraelectric logic;
a second die having CMOS based logic, wherein the second die is coupled to the first die in a 2.5D configuration or a 3D configuration, wherein the memory is coupled to the first die and/or the second die;
a power management unit including circuitry which is coupled to the first die and the second die, wherein the circuitry is to manage power of the first die and the second die based on a first throughput ratio of the ferroelectric logic or the paraelectric logic and a second throughput ratio of the CMOS based logic,
wherein the ferroelectric logic or the paraelectric logic includes at least three capacitors with first terminals to receive inputs and second terminals that are directly coupled to a node, wherein at least one capacitor of the at least three capacitors includes non-linear polar material, wherein the ferroelectric logic or the paraelectric logic includes a reset mechanism coupled to the node, wherein the reset mechanism is operable to reset charge on the node in a reset phase separate from an evaluation phase of the inputs, wherein the first die and the second die have an overlapping functionality, wherein the power management unit is operable to manage power of the overlapping functionality in the first die and the second die; and
a communication interface to allow the first die or the second die to communicate with another device.

### Claim 15 (depends on 14)

The system of claim 14, wherein the power management unit is to compute the first throughput ratio of the ferroelectric logic or the paraelectric logic, and wherein the power management unit is to compute the second throughput ratio of the CMOS based logic.

### Claim 16 (depends on 15)

The system of claim 15, wherein the power management unit is to throttle the CMOS based logic and to allocate additional power budget to the ferroelectric logic or the paraelectric logic based on the first throughput ratio being greater than the second throughput ratio.

### Claim 17 (depends on 15)

The system of claim 15, wherein the power management unit is to throttle the ferroelectric logic or the paraelectric logic and to allocate additional power to the CMOS based logic based on the second throughput ratio being greater than a scaled version of the first throughput ratio.

### Claim 18

A non-transitory machine-readable storage media having machine-readable instructions stored that when executed cause of one or more machines to perform a method, the method comprising:
computing a first throughput ratio of a ferroelectric logic or a paraelectric logic, wherein the ferroelectric logic or the paraelectric logic includes at least three capacitors with first terminals to receive inputs and second terminals that are directly coupled to a node, wherein at least one capacitor of the at least three capacitors includes non-linear polar material, wherein the ferroelectric logic or the paraelectric logic includes a reset mechanism coupled to the node, wherein the reset mechanism is operable to reset charge on the node in a reset phase separate from an evaluation phase of the inputs;
computing a second throughput ratio of a CMOS based logic; and
managing power of the ferroelectric logic or the paraelectric logic and the CMOS based logic based on the first throughput ratio and the second throughput ratio, wherein the CMOS based logic and the ferroelectric logic or the paraelectric logic have an overlapping functionality, wherein a power management unit is operable to manage power of the overlapping functionality in the CMOS based logic and the ferroelectric logic or the paraelectric logic.

### Claim 19 (depends on 18)

The non-transitory machine-readable storage media of claim 18 having further machine-readable instructions stored that when executed cause of the one or more machines to perform a further method, the further method comprising:
throttling the CMOS based logic and allocating additional power budget to the ferroelectric logic or the paraelectric logic based on the first throughput ratio being greater than the second throughput ratio; and
throttling the ferroelectric logic or the paraelectric logic and allocating additional power to the CMOS based logic based on the second throughput ratio being greater than a scaled version of the first throughput ratio.