# US 12,000,890 B2 · Electronic device and phase detector > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,000,890 B2 - Document ID: US12000890B2 - Status: Granted - Kind: B2 - Application number: 17/881,811 - Filed: 2022-08-05 - Published: 2024-02-08 - Granted: 2024-06-04 - Earliest claimed: 2022-08-05 - Assignees: Nanya Technology Corporation - Applicants: Nanya Technology Corporation - Inventors: Wu-Der Yang - Web page: https://patentgrep.com/patent/US12000890B2 ## CPC - G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)} - H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) - H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor} - H03L 7/0816: {the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract An electronic device including a phase detector is provided. The phase detector includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first equalizer device. The first transistor has a first input terminal configured to receive a first signal. The second transistor has a second input terminal configured to receive a second signal. The third transistor is electrically connected to the first transistor and has a first output terminal. The fourth transistor is electrically connected to the second transistor and has a second output terminal. The first equalizer device is connected between the first output terminal and the second input terminal. ## Claims ### Claim 1 A phase detector, comprising: a first transistor having a first input terminal configured to receive a first signal; a second transistor having a second input terminal configured to receive a second signal; a third transistor electrically connected to the first transistor and having a first output terminal; a fourth transistor electrically connected to the second transistor and having a second output terminal; and a first equalizer device connected between the first output terminal and the second input terminal; wherein the first equalizer is configured to: (i) during an equalization period, be turned on to equalize voltages at the first output terminal and the second output terminal; and (ii) during a sensing period, be turned off to electrically disconnect the first output terminal and the second output terminal wherein the first signal and the second signal have a same frequency, and wherein the first signal has a first phase and the second signal has a second phase; wherein, during the sensing period, if the first phase of the first signal is later than the second phase of the second signal, the second transistor and the fourth transistor pull down a voltage at the second output terminal to a ground. ### Claim 2 (depends on 1) The phase detector of claim 1, wherein, during the sensing period, if the first phase of the first signal is ahead of the second phase of the second signal, the first transistor and the third transistor pull down a voltage at the first output terminal to the ground. ### Claim 3 (depends on 1) The phase detector of claim 1, wherein the first transistor has a gate as the first input terminal, a source electrically connected to a ground, and a drain electrically connected to a source of the third transistor. ### Claim 4 (depends on 3) The phase detector of claim 3, wherein the second transistor has a gate as the second input terminal, a source electrically connected to the ground, and a drain electrically connected to a source of the fourth transistor. ### Claim 5 (depends on 1) The phase detector of claim 1, wherein the third transistor has a gate electrically connected to the second output terminal, a source electrically connected to a source of the first transistor, and a drain as the first output terminal. ### Claim 6 (depends on 5) The phase detector of claim 5, wherein the fourth transistor has a gate electrically connected to the first output terminal, a source electrically connected to a source of the first transistor, and a drain as the second output terminal. ### Claim 7 (depends on 6) The phase detector of claim 6, further comprising a second equalizer device connected between the gate of the third transistor and the gate of the fourth transistor. ### Claim 8 (depends on 7) The phase detector of claim 7, wherein the first equalizer device and the second equalizer device are electrically connected in parallel but are in different layout locations. ### Claim 9 (depends on 1) The phase detector of claim 1, further comprising a fourth equalizer device connected between a drain of the first transistor and a drain of the second transistor. ### Claim 10 A phase detector, comprising: a first transistor having a first input terminal configured to receive a first signal; a second transistor having a second input terminal configured to receive a second signal; a third transistor electrically connected to the first transistor and having a first output terminal; a fourth transistor electrically connected to the second transistor and having a second output terminal; and a first equalizer device connected between the first output terminal and the second input terminal; wherein the first equalizer is configured to: (i) during an equalization period, be turned on to equalize voltages at the first output terminal and the second output terminal; and (ii) during a sensing period, be turned off to electrically disconnect the first output terminal and the second output terminal; wherein the first equalizer includes a first p-type transistor having a gate configured to receive the first signal, a drain connected to a drain of the first transistor, and a source connected to a drain of the second transistor; wherein, in response to the first signal, the first p-type transistor is turned on during the equalization period and turned off during the sensing period; wherein the first equalizer includes an inverter configured to invert the first signal, and a first n-type transistor and having a gate configured to receive the inverted first signal, a drain connected to a source of the first p-type transistor, and a source connected to a drain of the first p-type transistor. ### Claim 11 (depends on 10) The phase detector of claim 10, wherein, in response to the inverted first signal, the first n-type transistor is turned on during the equalization period and turned off during the sensing period. ### Claim 12 A phase detector, comprising: a first transistor having a first input terminal configured to receive a first signal; a second transistor having a second input terminal configured to receive a second signal; a third transistor electrically connected to the first transistor and having a first output terminal; a fourth transistor electrically connected to the second transistor and having a second output terminal; a first equalizer device connected between the first output terminal and the second input terminal; a fifth transistor having a gate electrically connected to the second output terminal, a source electrically connected to a supply voltage, and a drain electrically connected to the first output terminal; a sixth transistor having a gate electrically connected to the first output terminal, a source electrically connected to the supply voltage, and a drain electrically connected to the second output terminal; and a third equalizer device connected between the gate of the fifth transistor and the gate of the sixth transistor. ### Claim 13 (depends on 12) The phase detector of claim 12, wherein the first equalizer device and the third equalizer device are electrically connected in parallel but are in different layout locations.