# US 12,000,888 B2 · Integrated circuit including test circuit and method of manufacturing the same

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- Number: US 12,000,888 B2
- Document ID: US12000888B2
- Status: Granted
- Kind: B2
- Application number: 17/857,379
- Filed: 2022-07-05
- Published: 2023-02-16
- Granted: 2024-06-04
- Earliest claimed: 2021-08-11
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Changho Han; Mijeong Lim; Yuncheol Kim; Kwanghun Oh
- Web page: https://patentgrep.com/patent/US12000888B2

## CPC

- G01R 31/31725: {Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937)}
- G01R 31/3016: {Delay or race condition test, e.g. race hazard test}
- G01R 31/31715: {Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer}
- G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)}
- G01R 31/3173: Marginal testing
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318314: {Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages (simulation software G01R31/318357; emulators G06F11/261)}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- G01R 31/318513: {Test of Multi-Chip-Moduls}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit includes first to nth metal layers vertically stacked on a substrate, and a test circuit outputting a test result signal according to a characteristic of each of the first to nth metal layers. The test circuit includes first to nth test circuits for generating a plurality of clock signals. Each clock signal of the plurality of clock signal has a frequency according to a characteristic of a corresponding metal layer among the first to nth metal layers, and n is a natural number.

## Claims

### Claim 1

An integrated circuit comprising:
first to nth metal layers vertically stacked on a substrate; and
a test circuit configured to output a test result signal according to a characteristic of each of the first to nth metal layers,
wherein the test circuit comprises:
first to nth test circuits configured to generate a plurality of clock signals, each clock signal of the plurality of clock signals having a frequency according to a characteristic of a corresponding metal layer among the first to nth metal layers, and
wherein n is a natural number,
wherein each of the first to nth test circuits comprises a first ring oscillator and a second ring oscillator,
wherein a frequency of a first clock signal output from the first ring oscillator and a frequency of a second clock signal output from the second ring oscillator are different from each other,
wherein the first ring oscillator comprises a plurality of inverters connected with each other using a first test pattern formed in a corresponding metal layer of the first to nth metal layers,
wherein the second ring oscillator comprises a plurality of inverters connected with each other using a second test pattern formed in the corresponding metal layer of the first to nth metal layers, and
wherein an extension length of the first test pattern and an extension length of the second test pattern are different from each other.

### Claim 2 (depends on 1)

The integrated circuit of claim 1,
wherein the test circuit further comprises a common ring oscillator,
wherein the common ring oscillator comprises a plurality of inverters connected with each other using a common test pattern formed in one metal layer among the first to nth metal layers, and
wherein an extension length of the common test pattern is less than each of the extension length of the first test pattern and the extension length of the second test pattern.

### Claim 3 (depends on 1)

The integrated circuit of claim 1,
wherein the first ring oscillator further comprises a ground line which is adjacent to the first test pattern to electrically shield the first test pattern and receives a ground voltage.

### Claim 4 (depends on 1)

The integrated circuit of claim 1,
wherein the test circuit comprises:
a decoder configured to provide an enable signal to the first to nth test circuits in response to a selection signal;
a multiplexer configured to receive the plurality of clock signals from the first to nth test circuits, and output a clock signal in response to the selection signal; and
a frequency divider configured to output the test result signal by adjusting a frequency of the clock signal.

### Claim 5 (depends on 1)

The integrated circuit of claim 1,
wherein a width, in a first horizontal direction, of a pattern of a first metal layer among the first to nth metal layers is less than a width, in a second horizontal direction, of a pattern of an nth metal layer among the first to nth metal layers,
wherein the first metal layer is a lowest metal layer among the first to nth metal layers, and the nth metal layer is a highest metal layer among the first to nth metal layers, and
wherein the first horizontal direction is perpendicular to or parallel to the second horizontal direction.

### Claim 6 (depends on 1)

The integrated circuit of claim 1,
wherein a thickness, in a vertical direction, of a pattern of a first metal layer among the first to nth metal layers is less than a thickness, in the vertical direction, of a pattern of an nth metal layer among first to nth metal layers, and
wherein the first metal layer is a lowest metal layer among the first to nth metal layers, and the nth metal layer is a highest metal layer among the first to nth metal layers.

### Claim 7 (depends on 1)

The integrated circuit of claim 1,
wherein patterns of the first to nth metal layers comprise a same material as each other.

### Claim 8

An integrated circuit comprising a test circuit,
wherein the test circuit comprises:
a first ring oscillator comprising a plurality of inverters connected with each other using a first test pattern formed in a first metal layer among a plurality of metal layers that are vertically stacked on each other; and
a second ring oscillator comprising a plurality of inverters connected with each other using a second test pattern formed in the first metal layer,
wherein an extension length of the first test pattern of the first metal layer and an extension length of the second test pattern of the first metal layer are different from each other.

### Claim 9 (depends on 8)

The integrated circuit of claim 8,
wherein the test circuit further comprises:
a common ring oscillator which comprises a plurality of inverters connected with each other using a common test pattern formed in the first metal layer, and
wherein an extension length of the common test pattern is different from each of an extension length of the first test pattern and an extension length of the second test pattern.

### Claim 10 (depends on 8)

The integrated circuit of claim 8,
wherein the test circuit further comprises:
a common ring oscillator which comprises a plurality of inverters connected with each other using a common test pattern formed in a different layer, among the plurality of metal layers, from the first metal layer, and
wherein an extension length of the common test pattern is less than each of an extension length of the first test pattern and an extension length of the second test pattern.

### Claim 11 (depends on 8)

The integrated circuit of claim 8,
wherein the test circuit further comprises:
a third ring oscillator comprising a plurality of inverters connected with each other using a third test pattern formed in a second metal layer, among the plurality of metal layers, different from the first metal layer; and
a fourth ring oscillator comprising a plurality of inverters connected with each other using a fourth test pattern formed in the second metal layer, and
wherein an extension length of the third test pattern of the second metal layer and an extension length of the fourth test pattern of the second metal layer are different from each other.

### Claim 12 (depends on 8)

The integrated circuit of claim 8,
wherein the first ring oscillator outputs a first clock signal having a first frequency, and
wherein the second ring oscillator outputs a second clock signal having a second frequency different from the first frequency.

### Claim 13

A method of manufacturing an integrated circuit comprising a plurality of metal layers, the method comprising:
obtaining frequencies of test result signals from a plurality of ring oscillators in a plurality of test circuits, wherein each test circuit includes at least two ring oscillators having test patterns formed in a specific metal layer among the plurality of metal layers, and wherein the test patterns are different in extension lengths thereof; and
extracting a resistance value and a capacitance value of a pattern formed in the specific metal layer by performing machine learning on the frequencies of the test result signals.

### Claim 14 (depends on 13)

The method of claim 13,
wherein the obtaining of the frequencies of the test result signals and the extracting of the resistance value and the capacitance value of the pattern formed in the specific metal layer are performed on each of the plurality of metal layers.

### Claim 15 (depends on 13)

The method of claim 13, further comprising:
analyzing timing characteristics of the integrated circuit by using the extracted resistance value and the extracted capacitance value; and
detecting a defect of the integrated circuit based on a result of the analysis of the timing characteristics of the integrated circuit.

### Claim 16 (depends on 15)

The method of claim 15,
wherein the analyzing of the timing characteristics of the integrated circuit comprises:
correcting a preset resistance value and a preset capacitance value by using the extracted resistance value and the extracted capacitance value; and
calculating a delay time of signals input or output between circuit elements of the integrated circuit, by using the corrected resistance value and the corrected capacitance value.

### Claim 17 (depends on 13)

The method of claim 13,
wherein the obtaining of the frequencies of the test result signals comprises obtaining a frequency of a test result signal from a common ring oscillator which comprises common test patterns formed in a different metal layer from the specific metal layer among the plurality of metal layers.

### Claim 18 (depends on 17)

The method of claim 17,
wherein an extension length of the common test patterns is less than an extension length of the test patterns.