US 11,995,388 B2Granted

Integrated circuit and method of forming same

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsPo-Sheng Wang, Chao Yuan Cheng, Chien-Chi Tien, Yangsyu Lin

Life of this patent

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Abstract

An integrated circuit includes a first active region of a first set of transistors of a first type, a second active region of a second set of transistors of the first type, a third active region of a third set of transistors of the first type, a fourth active region of a fourth set of transistors of the first type and a fifth active region of a fifth set of transistors of a second type. The first, second, fourth and fifth active region have a first width in a second direction, and are on a first level. The third active region is on the first level, and has a second width different from the first width. The second active region is adjacent to the first boundary, and is separated from the first active region in the second direction. The fourth active region is adjacent to the second boundary.

Claims20

Dependent claims

An integrated circuit comprising:

a first active region of a first set of transistors of a first type, the first active region extending in a first direction, being in a first level, adjacent to a first boundary and having a first width in a second direction different from the first direction;
a second active region of a second set of transistors of the first type, the second active region extending in the first direction, being in the first level, adjacent to the first boundary, and separated from the first active region in the second direction, and having the first width;
a third active region of a third set of transistors of the first type, the third active region extending in the first direction, being in the first level, and adjacent to a second boundary, and having a second width different from the first width;
a fourth active region of a fourth set of transistors of the first type, the fourth active region extending in the first direction, being in the first level, adjacent to the second boundary, and separated from the third active region in the second direction, and having the second width;
and
a fifth active region of a fifth set of transistors of a second type different from the first type, the fifth active region extending in the first direction, being in the first level, between the second active region and the third active region, and having the first width.

3 more elements

An integrated circuit comprising:

a first region corresponding to a first circuit, the first region comprising:
a first boundary extending in a first direction;
a second boundary extending in the first direction;
a first active region of a first set of transistors of a first type, the first active region extending in the first direction, being in a first level, adjacent to the first boundary and having a first width in a second direction different from the first direction;
a second active region of a second set of transistors of the first type, the second active region extending in the first direction, being in the first level, and adjacent to the second boundary, and having a second width different from the first width;
a third active region of a third set of transistors of a second type different from the first type, the third active region extending in the first direction, being in the first level, being between the first active region and the second active region, and having the first width;
and
a fourth active region of a fourth set of transistors of the second type, the fourth active region extending in the first direction, being in the first level, and being between the third active region and the second active region and having the first width.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/317,690Filed 15 May 2023 · division
Priority: 5 Mar 2020
Published: US 2023/0297754 A121 Sep 2023
Granted: 28 May 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
H10D 84/907
Comprising field effect technology: cMOS gate arrays
H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts
G06F 2119/18
Details relating to the type or aim of the analysis or the optimisation: manufacturability analysis or optimisation for manufacturability

Family

Application62/985,391Us provisional application · filed 5 Mar 2020
Application17/031,547Parent of this division · filed 24 Sep 2020
US 2023/0297754 A1Pre-grant publication · published 21 Sep 2023
US 11,651,133 B2Parent of this division
US 2021/0279396 A1Published application
US 11,995,388 B2This patent

From the US filing history. Foreign family members aren’t listed.