Memory management
AssigneeMicron Technology, Inc.
InventorsHoria C. Simionescu, Chung Kuang Chin
Life of this patent
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Abstract
Managed units (MUs) of data can be stored on a memory device according to a slice-based layout. A slice of the slice-based layout can include a plurality of stripes, each of the stripes including respective partitions and respective MUs of data. A subset of the stripes each include a quantity of partitions and a first quantity of MUs of data. Another subset of the stripes each include a lesser quantity of partitions and a lesser quantity of MUs of data.
Claims18
A method, comprising:
- storing managed units (MUs) of data on a memory device according to a slice-based layout, wherein a slice of the slice-based layout comprises a plurality of stripes, wherein:
- each of the stripes comprises a respective plurality of partitions and a respective plurality of MUs of data,
- each stripe of a first subset of the stripes comprises a first quantity of partitions and a first quantity of MUs of data, and
- each stripe of a second subset of the stripes comprises a second quantity of partitions that is less than the first quantity of partitions and a second quantity of MUs of data that is less than the first quantity of MUs of data,
- translating an address of a target MU of data to a particular slice address, wherein translating the address of the target MU of data comprises dividing the address by a per-slice quantity of MUs of the slice-based layout to obtain the particular slice address.
An apparatus, comprising a management component of a memory system configured to:
- store managed units (MUs) of data and parity MUs on a memory device of the memory system, according to a slice-based layout such that each slice of the slice-based layout comprises:
- a plurality of partitions of the memory device;
- and
- a plurality of stripes, wherein each of the stripes comprises a respective plurality of MUs of data and a respective parity MU, wherein each MU of the stripe corresponds to a respective channel of the memory device, wherein:
- each stripe of a first subset of the stripes comprises a first quantity of MUs of data, and
- each stripe of a second subset of the stripes comprises a second quantity of MUs of data that is less than the first quantity of MUs of data;
- each stripe of the slice comprises a respective subset of the partitions;
- each stripe of the first subset comprises a first quantity of partitions;
- each stripe of the second subset comprises a second quantity of partitions that is less than the first quantity of partitions;
- and
- execute commands associated with each respective stripe according to a plurality of scheduling policies.
An apparatus, comprising a management component of a memory system configured to:
- store managed units (MUs) of data and parity MUs on a memory device of the memory system according to a stripe-based layout such that each stripe of the stripe-based layout comprises a plurality of partitions of the memory device, wherein:
- each partition of the memory device corresponds to more than one stripe, and
- each MU of data is associated with a respective stripe;
- and
- cause execution of commands associated with each respective stripe according to a plurality of scheduling policies,
- wherein the management component further comprises a respective plurality of first in first outs (FIFOs) for each channel of the memory device and a quantity of FIFOs for each channel of the memory device is equal to a quantity of stripes for each respective memory address.
A method, comprising:
- storing managed units (MUs) of data on a memory device according to a slice-based layout, wherein a slice of the slice-based layout comprises a plurality of stripes, wherein:
- each of the stripes comprises a respective plurality of partitions and a respective plurality of MUs of data,
- each stripe of a first subset of the stripes comprises a first quantity of partitions and a first quantity of MUs of data, and
- each stripe of a second subset of the stripes comprises a second quantity of partitions that is less than the first quantity of partitions and a second quantity of MUs of data that is less than the first quantity of MUs of data;
- translating an address of a target MU of data to a particular slice address;
- mapping the particular slice address to a particular physical super-slice address corresponding to a plurality of slices including a particular slice associated with the particular slice address.
Dependencies are inferred from the claim text.