# US 11,994,571 B2 · 5-PS-resolution waveform-capture-device on a field-programmable gate-array with dynamic phase-shifting > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,994,571 B2 - Document ID: US11994571B2 - Status: Granted - Kind: B2 - Application number: 17/676,340 - Filed: 2022-02-21 - Published: 2022-10-27 - Granted: 2024-05-28 - Earliest claimed: 2021-04-21 - Assignees: Ohio State Innovation Foundation; Potomac Research LLC - Applicants: Ohio State Innovation Foundation; Potomac Research LLC - Inventors: Noeloikeau Charlot; Daniel Gauthier; Andrew Pomerance - Web page: https://patentgrep.com/patent/US11994571B2 ## CPC - G01R 35/005: {Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references (G01R33/0035, G01R35/002 take precedence)} - G01R 13/02: for displaying measured electric variables in digital form - G01R 13/0218: {Circuits therefor} - G04F 10/005: {Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60)} - H03K 19/173: using elementary logic circuits as components - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G04F: TIME-INTERVAL MEASURING (measuring pulse characteristics G01R, e.g. G01R29/02; in radar or like systems G01S) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A waveform capture device (WCD) is a flexible measurement system capable of recording complex digital signals on trillionth-of-a-second (ps) time scales. The WCD may be implemented via modular code on an off-the-shelf field-programmable gate-array (FPGA), and incorporates both time-to-digital converter (TDC) and digital storage oscilloscope (DSO) functionality. The device captures a waveform by taking snapshots of a signal as it propagates down an ultra-fast transmission line known as a carry chain (CC). It may be calibrated via a dynamic phase-shifting (DPS) method that requires substantially less data and resources than conventional techniques. ## Claims ### Claim 1 A device comprising: a time-to-digital converter (TDC); and a digital oscilloscope (DO), wherein the device is a waveform-capture-device (WCD), and wherein the WCD uses a plurality of carry-chains (CCs) to capture a digital waveform without encoding the digital waveform. ### Claim 2 (depends on 1) The device of claim 1, further comprising a tapped delay line (TDL) comprising a plurality of registers and the plurality of CCs. ### Claim 3 (depends on 1) The device of claim 1, wherein the WCD is a 5 ps-resolution TDC/ultra-fast DO hybrid. ### Claim 4 (depends on 1) The device of claim 1, wherein the WCD is implemented on a field-programmable gate-array (FPGA). ### Claim 5 (depends on 1) The device of claim 1, wherein the WCD is configured to measure complex GHz frequency waveforms at picosecond time intervals. ### Claim 6 (depends on 1) The device of claim 1, wherein the WCD is calibrated via a dynamic phase-shifting (DPS) process that adjusts a phase of a stable on-board clock. ### Claim 7 (depends on 2) The device of claim 2, wherein each CC is used to buffer an input signal and wherein the registers are used to capture a waveform of the input signal on an edge of a clock. ### Claim 8 (depends on 7) The device of claim 7, wherein each CC comprises at least one carry-element (CE) that passes the input signal to another CE after a time-delay. ### Claim 9 A method of calibrating a waveform-capture-device (WCD), the method comprising using dynamic phase shifting (DPS) for discrete measurement, wherein the DPS uses dynamic-phase calibration (DPC), and wherein the DPS generates ps-scale time-intervals without reconfiguring a field-programmable gate-array (FPGA). ### Claim 10 (depends on 9) The method of claim 9, wherein the DPS functions by adjusting the phase of a stable on-board clock, wherein the clock is a phase-lock loop (PLL). ### Claim 11 (depends on 9) The method of claim 9, wherein the WCD is a digital buffer and the DPC is a velocity calculation that measures the distance travelled down the digital buffer after a phase-shift. ### Claim 12 (depends on 9) The method of claim 9, wherein for the discrete measurement, a capture time is incrementally delayed in discrete intervals via the DPS, and an input signal is repeatedly generated and measured once after every accumulated phase shift, thereby allowing for calibration of a carry speed. ### Claim 13 A waveform-capture-device (WCD) comprising: a time-to-digital converter (TDC); a digital oscilloscope (DO); and a tapped delay line (TDL) comprising a plurality of registers and a plurality of carry-chains (CCs), wherein the CCs are configured to capture a digital waveform without encoding the digital waveform, wherein each CC is used to buffer an input signal and wherein the registers are used to capture a waveform of the input signal on an edge of a clock, and wherein each CC comprises at least one carry-element (CD) that passes the input signal to another CE after a time-delay. ### Claim 14 (depends on 13) The device of claim 13, wherein the WCD is implemented on a field-programmable gate-array (FPGA), wherein the WCD is configured to measure complex GHz frequency waveforms at picosecond time intervals, and wherein the WCD is calibrated via a dynamic phase-shifting (DPS) process that adjusts a phase of a stable on-board clock. ### Claim 15 (depends on 14) The device of claim 14, wherein the DPS uses dynamic-phase calibration (DPC) and wherein the DPS functions by adjusting the phase of a stable on-board clock, wherein the clock is a phase-lock loop (PLL).