# US 11,994,559 B2 · Tests for integrated circuit (IC) chips

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- Number: US 11,994,559 B2
- Document ID: US11994559B2
- Status: Granted
- Kind: B2
- Application number: 17/871,205
- Filed: 2022-07-22
- Published: 2023-05-11
- Granted: 2024-05-28
- Earliest claimed: 2021-11-08
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lakshmanan Balasubramanian; Rubin Parekhji; Kalyan Chakravarthi Chekuri; Swathi G
- Web page: https://patentgrep.com/patent/US11994559B2

## CPC

- G01R 31/31835: {Analysis of test coverage or failure detectability}
- G01R 31/318307: {computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging}
- G01R 31/318357: {Simulation (computer simulation of digital circuits G06F30/3308)}
- G06F 30/30: Circuit design
- G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method for evaluating tests for fabricated integrated circuit (IC) chips includes providing, design for fault injection (DfFI) instances of an IC design that characterize activatable states of controllable elements in an IC chip based on the IC design. The method also includes fault simulating the IC design a corresponding identified test suite to determine a signature for faults and simulating the IC design with the DfFI instances activated to determine a signature for the DfFI instances. The method includes generating a DfFI-fault equivalence dictionary based on a comparison of the signature of the faults and DfFI instances and generating tests for a fabricated IC chip based on the IC design. The method includes receiving test result data characterizing the tests being applied against the fabricated IC chip with the DfFI instances activated and analyzing the test result data to determine an ability of the tests to detect the faults.

## Claims

### Claim 1

A method for evaluating tests for fabricated integrated circuit (IC) chips comprising:
providing, by an IC fault engine operating on a computing platform, design for fault injection (DfFI) instances of an IC design that characterize activatable states of controllable elements in an IC chip based on the IC design;
fault simulating, by an analog fault simulator (AFS) operating on the computing platform, the IC design and a corresponding identified test suite to determine a signature for faults;
simulating, by a circuit simulator operating on the computing platform, the IC design with the DfFI instances activated to determine a signature for the DfFI instances;
generating, by the IC fault engine, a DfFI-fault equivalence dictionary based on a comparison of the signature of the faults and the signatures of the DfFI instances;
generating and/or managing, by an IC test engine operating on the computing platform, tests for a fabricated IC chip that is based on the IC design;
receiving, by the IC test engine, test result data that characterizes the tests being applied against the fabricated IC chip based on the IC design with the DfFI instances activated; and
analyzing, by the IC test engine, the test result data to determine an ability of the tests to detect the faults.

### Claim 2 (depends on 1)

The method of claim 1, further comprising identifying, by the IC test engine operating on the computing platform, extra parameter controls that control parameters of an analog component of the IC design that are employable as a subset of the controllable elements for the DfFI instances.

### Claim 3 (depends on 2)

The method of claim 2, wherein tuning parameters of the controllable elements are digitally controlled.

### Claim 4 (depends on 3)

The method of claim 3, wherein the analog component comprises a low dropout (LDO) voltage regulator, and parameters controlled by the extra parameter controls at least one of a output voltage, reference voltage, bias current, gain and a bandwidth of an error amplifier of the LDO voltage regulator.

### Claim 5 (depends on 3)

The method of claim 3, further comprising selecting design for testability (DFT) elements in the IC design that are controllable to test the analog component of the IC chip, wherein the DFT elements are employable as a subset of the controllable elements for the DfFI instances.

### Claim 6 (depends on 5)

The method of claim 5, wherein the DFT elements are controllable by an analog test bus.

### Claim 7 (depends on 6)

The method of claim 6, wherein the analog component includes a voltage regulator, and the DFT elements comprise switches for measuring voltage and current on nodes and branches respectively of the voltage regulator.

### Claim 8 (depends on 1)

The method of claim 1, wherein the fabricated IC chip is a fault free fabricated IC chip.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
analyzing, by the IC test engine, the DfFI-fault equivalence dictionary to determine a fault coverage of the DfFI-fault equivalence dictionary; and
modifying the IC design to add additional controllable elements to the IC design to increase a number of DfFI instances in response to determining that the fault coverage of the DfFI-fault equivalence is below a fault coverage threshold.

### Claim 10 (depends on 1)

The method of claim 1, further comprising tuning the tests to remove redundant and/or unnecessary tests for the IC chip.

### Claim 11 (depends on 1)

The method of claim 1, further comprising analyzing the tests to determine a fault coverage of the tests.

### Claim 12 (depends on 11)

The method of claim 11, further comprising at least one of adding additional tests and modifying the IC design to increase the DfFI instances in response to determining that the fault coverage is below a fault coverage threshold.

### Claim 13 (depends on 11)

The method of claim 11, further comprising, releasing the IC design for volume fabrication of IC chips based on a determination that the fault coverage of the tests meets a fault coverage threshold.

### Claim 14

A system for evaluating tests for integrated circuit (IC) chips, the system comprising:
a non-transitory memory for storing machine readable instructions; and
a processing unit for accessing the non-transitory memory and executing the machine readable instructions, the machine readable instructions comprising:
an IC fault engine configured to:
provide design for fault injection (DfFI) instances of an IC design that characterize activatable states of controllable elements in an IC chip based on the IC design;
generate a fault universe based on data from an analog fault simulator (AFS) characterizing faults, tests and signatures of the faults;
generate a DfFI universe based on data from a circuit simulator characterizing signatures of the DfFI instances; and
generate a DfFI-fault equivalence dictionary based on a comparison of the signature of the faults and the signatures of the DfFI instances; and
an IC test engine configured to:
generate and/or manage tests for a fabricated IC chip that is based on the IC design;
receive test result data that characterizes the tests being applied against the fabricated IC chip based on the IC design with the DfFI instances activated; and
analyze the test result data to determine an ability of the tests to detect the faults.

### Claim 15 (depends on 14)

The system of claim 14, further comprising automatic test equipment (ATE) coupled to the fabricated IC chip, wherein the ATE applies the tests to the fabricated IC chip with the DfFI instances activated and provides the test result data to the IC test engine.

### Claim 16 (depends on 14)

The system of claim 14, wherein the IC test engine is further configured to:
identify tuning parameters that are digitally controlled to control parameters of an analog component of the IC design that are employable as a first subset of the controllable elements for the DfFI instances; and
select design for testability (DFT) elements in the IC design that are controllable through an analog test bus to test the analog component of the IC chip that are employable as a second subset of the controllable elements for the DfFI instances.

### Claim 17 (depends on 14)

The system of claim 14, wherein the fabricated IC chip is a fault free fabricated IC chip.

### Claim 18 (depends on 14)

The system of claim 14, wherein the IC test engine is further configured to analyze the DfFI-fault equivalence dictionary to determine a fault coverage of the DfFI-fault equivalence dictionary.

### Claim 19 (depends on 14)

The system of claim 14, wherein the IC test engine analyzes the tests to determine a fault coverage of the tests.

### Claim 20 (depends on 19)

The system of claim 19, wherein the IC design is released by the IC test engine for volume fabrication of IC chips in response to determining the fault coverage meets a fault coverage threshold.